Lines Matching +full:tx +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
53 * Number of TX queues.
122 * TXDONE_TXRING: Tx ring transmit done interrupt.
128 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
129 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
130 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
131 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
133 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
134 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
135 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
136 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
169 * TXDONE_TXRING: Tx ring transmit done interrupt.
175 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
176 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
177 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
178 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
180 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
181 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
182 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
183 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
218 * KICK_DECRYPT: Kick decryption engine, self-clear.
228 * CSR11: Back-off control register.
229 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
230 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
267 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
287 * CFP: ASIC is in contention-free period.
365 * TXCSR0: TX Control Register.
366 * KICK_TX: Kick tx ring.
378 * TXCSR1: TX Configuration Register.
391 * TXCSR2: Tx descriptor configuration register.
392 * TXD_SIZE: Tx descriptor size, default is 48.
393 * NUM_TXD: Number of tx entries in ring.
404 * TXCSR3: TX Ring Base address register.
410 * TXCSR4: TX Atim Ring Base address register.
416 * TXCSR5: TX Prio Ring Base address register.
435 * TXCSR8: CCK Tx BBP register.
448 * TXCSR9: OFDM TX BBP registers
545 * RX_TRESHOLD: Rx threshold in dw to start pci access
547 * TX_TRESHOLD: Tx threshold in dw to start pci access
550 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
589 * CNT5: Tx FIFO underrun count.
647 * KICK_RX: Kick one-shot rx in one-shot rx mode.
648 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
650 * AUTO_TXBBP: Auto tx logic access bbp control register.
665 * RALINKCSR: Ralink Rx auto-reset BBCR.
751 * TXPTR: Current Tx ring address.
761 * TXACKCSR0: TX ACK timeout.
767 * ACKCNT0: TX ACK timeout count.
802 * FIFOCSR0: TX FIFO pointer.
809 * BCNCSR1: Tx BEACON offset time control register.
818 * MACCSR2: TX_PE to RX_PE turn-around time control register
891 * KICK_ENCRYPT: Kick encryption engine, self-clear.
901 * BBPCSR1: BBP TX configuration.
945 * UARTCSR0: UART1 TX register.
949 * UART2CSR0: UART2 TX register.
969 * R2: TX antenna control
1023 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
1024 * DYN_TXAGC: Dynamic TX AGC control.
1041 * CCK_TX_POWER: CCK TX power compensation.
1072 * RSSI <-> dBm offset calibration
1084 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1136 * Word6-9: Key
1198 * Word6-9: Key