Lines Matching +full:tx +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
32 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
41 /* Tx FIFO default settings */
130 u32 auto_negotiation_advertisement; /* Auto-negotiation
182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
190 /* 14-bit maximum frame length. The MAC receive logic */
196 /* 12-bit receive FIFO section-empty threshold */
198 /* 12-bit receive FIFO section-full threshold */
200 /* 12-bit transmit FIFO section-empty threshold */
202 /* 12-bit transmit FIFO section-full threshold */
204 /* 12-bit receive FIFO almost-empty threshold */
206 /* 12-bit receive FIFO almost-full threshold */
208 /* 12-bit transmit FIFO almost-empty threshold */
210 /* 12-bit transmit FIFO almost-full threshold */
212 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
214 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
217 /* Bit[15:0]—16-bit holdoff quanta */
254 /* IETF MIB (MIB-II) Object Support */
422 /* mSGDMA Tx Dispatcher address space */
433 /* Tx ring buffer */
443 /* RX/TX MAC FIFO configs */
466 /* Tx path protection */
472 int phy_addr; /* PHY's MDIO address, -1 for autodetection */