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/Linux-v5.4/Documentation/devicetree/bindings/net/can/
Dxilinx_can.txt2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
15 - "can_clk", "pclk" (For CANPS),
[all …]
/Linux-v5.4/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
38 /* ----------------------------
40 * ----------------------------
48 /* ----------------------------
50 * ----------------------------
69 /* ----------------------------
71 * ----------------------------
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/Linux-v5.4/Documentation/devicetree/bindings/net/
Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
12 "tx_csr": xDMA Tx dispatcher control and status space region
13 "tx_desc": MSGDMA Tx dispatcher descriptor space region
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
[all …]
Dti,dp83867.txt1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
11 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
14 Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
19 should use "rgmii-id" if internal delays are desired as this may be
23 - ti,min-output-impedance - MAC Interface Impedance control to set
26 - ti,max-output-impedance - MAC Interface Impedance control to set
29 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
18 - $ref: /schemas/types.yaml#definitions/uint8-array
19 - items:
20 - minItems: 6
25 mac-address:
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/Linux-v5.4/include/linux/
Dqcom-geni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
29 * struct geni_se - GENI Serial Engine
178 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
237 * geni_se_read_proto() - Read the protocol configured for a serial engine
246 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
252 * geni_se_setup_m_cmd() - Setup the primary sequencer
265 writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
269 * geni_se_setup_s_cmd() - Setup the secondary sequencer
281 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
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/Linux-v5.4/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc.txt11 - snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12 * #address-cells: should be 1.
13 * #size-cells: should be 0.
16 child-nodes with each child-node representing a supported slot. There should
23 property is 0 to (num-slots -1), where num-slots is the value
24 specified by the num-slots property.
26 * bus-width: as documented in mmc core bindings.
28 * wp-gpios: specifies the write protect gpio line. The format of the
30 for write-protect, this property is optional.
32 * disable-wp: If the wp-gpios property isn't present then (by default)
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/Linux-v5.4/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "intel,socfpga-agilex";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
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/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dfsl,esai.txt3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
16 - reg : Offset and length of the register set for the device.
18 - interrupts : Contains the spdif interrupt.
20 - dmas : Generic dma devicetree binding as described in
23 - dma-names : Two dmas have to be defined, "tx" and "rx".
25 - clocks : Contains an entry for each entry in clock-names.
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/Linux-v5.4/drivers/net/ethernet/sgi/
Dmeth.h3 * snull.h -- definitions for the network module
20 #define TX_RING_ENTRIES 64 /* 64-512?*/
27 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
35 /* tx status vector is written over tx command header upon
48 * It consists of header, 0-3 concatination
56 u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
59 u64 data_len:16; /*Length of valid data in bytes-1*/
64 u64 len:16; /*length of buffer data - 1*/
107 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
109 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
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/Linux-v5.4/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
17 evm_1v8_sw: fixedregulator-evm_1v8 {
18 compatible = "regulator-fixed";
19 regulator-name = "evm_1v8";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
[all …]
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
[all …]
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/Linux-v5.4/drivers/i2c/busses/
Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
54 * @tx_pos: Current pos in TX message
59 * @endianness: big/little-endian byte order
87 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
[all …]
Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
175 * struct dw_i2c_dev - private i2c-designware data
178 * @cmd_complete: tx completion indicator
185 * @msg_write_idx: the element index of the current tx message in the msgs
187 * @tx_buf_len: the length of the current tx buffer
188 * @tx_buf: the current tx buffer
199 * @tx_fifo_depth: depth of the hardware tx fifo
200 * @rx_fifo_depth: depth of the hardware rx fifo
201 * @rx_outstanding: current master-rx elements in tx fifo
218 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
[all …]
/Linux-v5.4/drivers/spi/
Dspi-dw.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
16 #include "spi-dw.h"
39 struct dw_spi *dws = file->private_data; in dw_spi_show_regs()
48 len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, in dw_spi_show_regs()
49 "%s registers:\n", dev_name(&dws->master->dev)); in dw_spi_show_regs()
50 len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, in dw_spi_show_regs()
52 len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, in dw_spi_show_regs()
54 len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, in dw_spi_show_regs()
56 len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, in dw_spi_show_regs()
[all …]
Dspi-pic32.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
52 #define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
60 #define CTRL_CKE BIT(8) /* Tx on falling edge */
61 #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
75 #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
88 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
89 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
101 u32 fifo_n_byte; /* FIFO depth in bytes */
105 u32 speed_hz; /* spi-clk rate */
[all …]
/Linux-v5.4/arch/nios2/boot/dts/
D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
/Linux-v5.4/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/net/ti-dp83867.h>
133 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
156 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
158 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
170 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
171 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
172 struct device_node *of_node = dev->of_node; in dp83867_of_init()
176 return -ENODEV; in dp83867_of_init()
179 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
[all …]
/Linux-v5.4/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu102-revB.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2018, Xilinx, Inc.
10 #include "zynqmp-zcu102-revA.dts"
14 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
18 phy-handle = <&phyc>;
21 ti,rx-internal-delay = <0x8>;
22 ti,tx-internal-delay = <0xa>;
23 ti,fifo-depth = <0x1>;
24 ti,dp83867-rxctrl-strap-quirk;
27 /delete-node/ phy@21;
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