Lines Matching +full:tx +full:- +full:fifo +full:- +full:depth
1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
11 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
14 Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
19 should use "rgmii-id" if internal delays are desired as this may be
23 - ti,min-output-impedance - MAC Interface Impedance control to set
26 - ti,max-output-impedance - MAC Interface Impedance control to set
29 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
36 - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
40 - ti,sgmii-ref-clock-output-enable - This denotes which
41 SGMII configuration is used (4 or 6-wire modes).
45 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
46 exclusive. When both properties are present ti,max-output-impedance
54 ethernet-phy@0 {
56 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
57 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
58 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;