1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 - 2014 Xilinx 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 compatible = "arm,cortex-a9"; 17 device_type = "cpu"; 18 reg = <0>; 19 clocks = <&clkc 3>; 20 clock-latency = <1000>; 21 cpu0-supply = <®ulator_vccpint>; 22 operating-points = < 23 /* kHz uV */ 24 666667 1000000 25 333334 1000000 26 >; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <1>; 33 clocks = <&clkc 3>; 34 }; 35 }; 36 37 fpga_full: fpga-full { 38 compatible = "fpga-region"; 39 fpga-mgr = <&devcfg>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges; 43 }; 44 45 pmu@f8891000 { 46 compatible = "arm,cortex-a9-pmu"; 47 interrupts = <0 5 4>, <0 6 4>; 48 interrupt-parent = <&intc>; 49 reg = <0xf8891000 0x1000>, 50 <0xf8893000 0x1000>; 51 }; 52 53 regulator_vccpint: fixedregulator { 54 compatible = "regulator-fixed"; 55 regulator-name = "VCCPINT"; 56 regulator-min-microvolt = <1000000>; 57 regulator-max-microvolt = <1000000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 amba: amba { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 interrupt-parent = <&intc>; 67 ranges; 68 69 adc: adc@f8007100 { 70 compatible = "xlnx,zynq-xadc-1.00.a"; 71 reg = <0xf8007100 0x20>; 72 interrupts = <0 7 4>; 73 interrupt-parent = <&intc>; 74 clocks = <&clkc 12>; 75 }; 76 77 can0: can@e0008000 { 78 compatible = "xlnx,zynq-can-1.0"; 79 status = "disabled"; 80 clocks = <&clkc 19>, <&clkc 36>; 81 clock-names = "can_clk", "pclk"; 82 reg = <0xe0008000 0x1000>; 83 interrupts = <0 28 4>; 84 interrupt-parent = <&intc>; 85 tx-fifo-depth = <0x40>; 86 rx-fifo-depth = <0x40>; 87 }; 88 89 can1: can@e0009000 { 90 compatible = "xlnx,zynq-can-1.0"; 91 status = "disabled"; 92 clocks = <&clkc 20>, <&clkc 37>; 93 clock-names = "can_clk", "pclk"; 94 reg = <0xe0009000 0x1000>; 95 interrupts = <0 51 4>; 96 interrupt-parent = <&intc>; 97 tx-fifo-depth = <0x40>; 98 rx-fifo-depth = <0x40>; 99 }; 100 101 gpio0: gpio@e000a000 { 102 compatible = "xlnx,zynq-gpio-1.0"; 103 #gpio-cells = <2>; 104 clocks = <&clkc 42>; 105 gpio-controller; 106 interrupt-controller; 107 #interrupt-cells = <2>; 108 interrupt-parent = <&intc>; 109 interrupts = <0 20 4>; 110 reg = <0xe000a000 0x1000>; 111 }; 112 113 i2c0: i2c@e0004000 { 114 compatible = "cdns,i2c-r1p10"; 115 status = "disabled"; 116 clocks = <&clkc 38>; 117 interrupt-parent = <&intc>; 118 interrupts = <0 25 4>; 119 reg = <0xe0004000 0x1000>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 }; 123 124 i2c1: i2c@e0005000 { 125 compatible = "cdns,i2c-r1p10"; 126 status = "disabled"; 127 clocks = <&clkc 39>; 128 interrupt-parent = <&intc>; 129 interrupts = <0 48 4>; 130 reg = <0xe0005000 0x1000>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 }; 134 135 intc: interrupt-controller@f8f01000 { 136 compatible = "arm,cortex-a9-gic"; 137 #interrupt-cells = <3>; 138 interrupt-controller; 139 reg = <0xF8F01000 0x1000>, 140 <0xF8F00100 0x100>; 141 }; 142 143 L2: cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xF8F02000 0x1000>; 146 interrupts = <0 2 4>; 147 arm,data-latency = <3 2 2>; 148 arm,tag-latency = <2 2 2>; 149 cache-unified; 150 cache-level = <2>; 151 }; 152 153 mc: memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 uart0: serial@e0000000 { 159 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 160 status = "disabled"; 161 clocks = <&clkc 23>, <&clkc 40>; 162 clock-names = "uart_clk", "pclk"; 163 reg = <0xE0000000 0x1000>; 164 interrupts = <0 27 4>; 165 }; 166 167 uart1: serial@e0001000 { 168 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 169 status = "disabled"; 170 clocks = <&clkc 24>, <&clkc 41>; 171 clock-names = "uart_clk", "pclk"; 172 reg = <0xE0001000 0x1000>; 173 interrupts = <0 50 4>; 174 }; 175 176 spi0: spi@e0006000 { 177 compatible = "xlnx,zynq-spi-r1p6"; 178 reg = <0xe0006000 0x1000>; 179 status = "disabled"; 180 interrupt-parent = <&intc>; 181 interrupts = <0 26 4>; 182 clocks = <&clkc 25>, <&clkc 34>; 183 clock-names = "ref_clk", "pclk"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 }; 187 188 spi1: spi@e0007000 { 189 compatible = "xlnx,zynq-spi-r1p6"; 190 reg = <0xe0007000 0x1000>; 191 status = "disabled"; 192 interrupt-parent = <&intc>; 193 interrupts = <0 49 4>; 194 clocks = <&clkc 26>, <&clkc 35>; 195 clock-names = "ref_clk", "pclk"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 }; 199 200 gem0: ethernet@e000b000 { 201 compatible = "cdns,zynq-gem", "cdns,gem"; 202 reg = <0xe000b000 0x1000>; 203 status = "disabled"; 204 interrupts = <0 22 4>; 205 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 206 clock-names = "pclk", "hclk", "tx_clk"; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 }; 210 211 gem1: ethernet@e000c000 { 212 compatible = "cdns,zynq-gem", "cdns,gem"; 213 reg = <0xe000c000 0x1000>; 214 status = "disabled"; 215 interrupts = <0 45 4>; 216 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 217 clock-names = "pclk", "hclk", "tx_clk"; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 }; 221 222 sdhci0: mmc@e0100000 { 223 compatible = "arasan,sdhci-8.9a"; 224 status = "disabled"; 225 clock-names = "clk_xin", "clk_ahb"; 226 clocks = <&clkc 21>, <&clkc 32>; 227 interrupt-parent = <&intc>; 228 interrupts = <0 24 4>; 229 reg = <0xe0100000 0x1000>; 230 }; 231 232 sdhci1: mmc@e0101000 { 233 compatible = "arasan,sdhci-8.9a"; 234 status = "disabled"; 235 clock-names = "clk_xin", "clk_ahb"; 236 clocks = <&clkc 22>, <&clkc 33>; 237 interrupt-parent = <&intc>; 238 interrupts = <0 47 4>; 239 reg = <0xe0101000 0x1000>; 240 }; 241 242 slcr: slcr@f8000000 { 243 #address-cells = <1>; 244 #size-cells = <1>; 245 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 246 reg = <0xF8000000 0x1000>; 247 ranges; 248 clkc: clkc@100 { 249 #clock-cells = <1>; 250 compatible = "xlnx,ps7-clkc"; 251 fclk-enable = <0>; 252 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 253 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 254 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 255 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 256 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 257 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 258 "gem1_aper", "sdio0_aper", "sdio1_aper", 259 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 260 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 261 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 262 "dbg_trc", "dbg_apb"; 263 reg = <0x100 0x100>; 264 }; 265 266 rstc: rstc@200 { 267 compatible = "xlnx,zynq-reset"; 268 reg = <0x200 0x48>; 269 #reset-cells = <1>; 270 syscon = <&slcr>; 271 }; 272 273 pinctrl0: pinctrl@700 { 274 compatible = "xlnx,pinctrl-zynq"; 275 reg = <0x700 0x200>; 276 syscon = <&slcr>; 277 }; 278 }; 279 280 dmac_s: dmac@f8003000 { 281 compatible = "arm,pl330", "arm,primecell"; 282 reg = <0xf8003000 0x1000>; 283 interrupt-parent = <&intc>; 284 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 285 "dma4", "dma5", "dma6", "dma7"; 286 interrupts = <0 13 4>, 287 <0 14 4>, <0 15 4>, 288 <0 16 4>, <0 17 4>, 289 <0 40 4>, <0 41 4>, 290 <0 42 4>, <0 43 4>; 291 #dma-cells = <1>; 292 #dma-channels = <8>; 293 #dma-requests = <4>; 294 clocks = <&clkc 27>; 295 clock-names = "apb_pclk"; 296 }; 297 298 devcfg: devcfg@f8007000 { 299 compatible = "xlnx,zynq-devcfg-1.0"; 300 reg = <0xf8007000 0x100>; 301 interrupt-parent = <&intc>; 302 interrupts = <0 8 4>; 303 clocks = <&clkc 12>; 304 clock-names = "ref_clk"; 305 syscon = <&slcr>; 306 }; 307 308 global_timer: timer@f8f00200 { 309 compatible = "arm,cortex-a9-global-timer"; 310 reg = <0xf8f00200 0x20>; 311 interrupts = <1 11 0x301>; 312 interrupt-parent = <&intc>; 313 clocks = <&clkc 4>; 314 }; 315 316 ttc0: timer@f8001000 { 317 interrupt-parent = <&intc>; 318 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 319 compatible = "cdns,ttc"; 320 clocks = <&clkc 6>; 321 reg = <0xF8001000 0x1000>; 322 }; 323 324 ttc1: timer@f8002000 { 325 interrupt-parent = <&intc>; 326 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 327 compatible = "cdns,ttc"; 328 clocks = <&clkc 6>; 329 reg = <0xF8002000 0x1000>; 330 }; 331 332 scutimer: timer@f8f00600 { 333 interrupt-parent = <&intc>; 334 interrupts = <1 13 0x301>; 335 compatible = "arm,cortex-a9-twd-timer"; 336 reg = <0xf8f00600 0x20>; 337 clocks = <&clkc 4>; 338 }; 339 340 usb0: usb@e0002000 { 341 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 342 status = "disabled"; 343 clocks = <&clkc 28>; 344 interrupt-parent = <&intc>; 345 interrupts = <0 21 4>; 346 reg = <0xe0002000 0x1000>; 347 phy_type = "ulpi"; 348 }; 349 350 usb1: usb@e0003000 { 351 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 352 status = "disabled"; 353 clocks = <&clkc 29>; 354 interrupt-parent = <&intc>; 355 interrupts = <0 44 4>; 356 reg = <0xe0003000 0x1000>; 357 phy_type = "ulpi"; 358 }; 359 360 watchdog0: watchdog@f8005000 { 361 clocks = <&clkc 45>; 362 compatible = "cdns,wdt-r1p2"; 363 interrupt-parent = <&intc>; 364 interrupts = <0 9 1>; 365 reg = <0xf8005000 0x1000>; 366 timeout-sec = <10>; 367 }; 368 }; 369}; 370
