1* Synopsys Designware Mobile Storage Host Controller
2
3The Synopsys designware mobile storage host controller is used to interface
4a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
5differences between the core mmc properties described by mmc.txt and the
6properties used by the Synopsys Designware Mobile Storage Host Controller.
7
8Required Properties:
9
10* compatible: should be
11	- snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12* #address-cells: should be 1.
13* #size-cells: should be 0.
14
15# Slots (DEPRECATED): The slot specific information are contained within
16  child-nodes with each child-node representing a supported slot. There should
17  be atleast one child node representing a card slot. The name of the child node
18  representing the slot is recommended to be slot@n where n is the unique number
19  of the slot connected to the controller. The following are optional properties
20  which can be included in the slot child node.
21
22	* reg: specifies the physical slot number. The valid values of this
23	  property is 0 to (num-slots -1), where num-slots is the value
24	  specified by the num-slots property.
25
26	* bus-width: as documented in mmc core bindings.
27
28	* wp-gpios: specifies the write protect gpio line. The format of the
29	  gpio specifier depends on the gpio controller. If a GPIO is not used
30	  for write-protect, this property is optional.
31
32	* disable-wp: If the wp-gpios property isn't present then (by default)
33	  we'd assume that the write protect is hooked up directly to the
34	  controller's special purpose write protect line (accessible via
35	  the WRTPRT register).  However, it's possible that we simply don't
36	  want write protect.  In that case specify 'disable-wp'.
37	  NOTE: This property is not required for slots known to always
38	  connect to eMMC or SDIO cards.
39
40Optional properties:
41
42* resets: phandle + reset specifier pair, intended to represent hardware
43  reset signal present internally in some host controller IC designs.
44  See Documentation/devicetree/bindings/reset/reset.txt for details.
45
46* reset-names: request name for using "resets" property. Must be "reset".
47	(It will be used together with "resets" property.)
48
49* clocks: from common clock binding: handle to biu and ciu clocks for the
50  bus interface unit clock and the card interface unit clock.
51
52* clock-names: from common clock binding: Shall be "biu" and "ciu".
53  If the biu clock is missing we'll simply skip enabling it.  If the
54  ciu clock is missing we'll just assume that the clock is running at
55  clock-frequency.  It is an error to omit both the ciu clock and the
56  clock-frequency.
57
58* clock-frequency: should be the frequency (in Hz) of the ciu clock.  If this
59  is specified and the ciu clock is specified then we'll try to set the ciu
60  clock to this at probe time.
61
62* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
63  specified, the default value of the fifo size is determined from the
64  controller registers.
65
66* card-detect-delay: Delay in milli-seconds before detecting card after card
67  insert event. The default value is 0.
68
69* data-addr: Override fifo address with value provided by DT. The default FIFO reg
70  offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by
71  driver. If the controller does not follow this rule, please use this property
72  to set fifo address in device tree.
73
74* fifo-watermark-aligned: Data done irq is expected if data length is less than
75  watermark in PIO mode. But fifo watermark is requested to be aligned with data
76  length in some SoC so that TX/RX irq can be generated with data done irq. Add this
77  watermark quirk to mark this requirement and force fifo watermark setting
78  accordingly.
79
80* vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
81  specified we'll defer probe until we can find this regulator.
82
83* dmas: List of DMA specifiers with the controller specific format as described
84  in the generic DMA client binding. Refer to dma.txt for details.
85
86* dma-names: request names for generic DMA client binding. Must be "rx-tx".
87  Refer to dma.txt for details.
88
89Aliases:
90
91- All the MSHC controller nodes should be represented in the aliases node using
92  the following format 'mshc{n}' where n is a unique number for the alias.
93
94Example:
95
96The MSHC controller node can be split into two portions, SoC specific and
97board specific portions as listed below.
98
99	dwmmc0@12200000 {
100		compatible = "snps,dw-mshc";
101		clocks = <&clock 351>, <&clock 132>;
102		clock-names = "biu", "ciu";
103		reg = <0x12200000 0x1000>;
104		interrupts = <0 75 0>;
105		#address-cells = <1>;
106		#size-cells = <0>;
107		data-addr = <0x200>;
108		fifo-watermark-aligned;
109		resets = <&rst 20>;
110		reset-names = "reset";
111	};
112
113[board specific internal DMA resources]
114
115	dwmmc0@12200000 {
116		clock-frequency = <400000000>;
117		clock-freq-min-max = <400000 200000000>;
118		broken-cd;
119		fifo-depth = <0x80>;
120		card-detect-delay = <200>;
121		vmmc-supply = <&buck8>;
122		bus-width = <8>;
123		cap-mmc-highspeed;
124		cap-sd-highspeed;
125	};
126
127[board specific generic DMA request binding]
128
129	dwmmc0@12200000 {
130		clock-frequency = <400000000>;
131		clock-freq-min-max = <400000 200000000>;
132		broken-cd;
133		fifo-depth = <0x80>;
134		card-detect-delay = <200>;
135		vmmc-supply = <&buck8>;
136		bus-width = <8>;
137		cap-mmc-highspeed;
138		cap-sd-highspeed;
139		dmas = <&pdma 12>;
140		dma-names = "rx-tx";
141	};
142