Lines Matching +full:tx +full:- +full:fifo +full:- +full:depth
11 - snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12 * #address-cells: should be 1.
13 * #size-cells: should be 0.
16 child-nodes with each child-node representing a supported slot. There should
23 property is 0 to (num-slots -1), where num-slots is the value
24 specified by the num-slots property.
26 * bus-width: as documented in mmc core bindings.
28 * wp-gpios: specifies the write protect gpio line. The format of the
30 for write-protect, this property is optional.
32 * disable-wp: If the wp-gpios property isn't present then (by default)
36 want write protect. In that case specify 'disable-wp'.
46 * reset-names: request name for using "resets" property. Must be "reset".
52 * clock-names: from common clock binding: Shall be "biu" and "ciu".
55 clock-frequency. It is an error to omit both the ciu clock and the
56 clock-frequency.
58 * clock-frequency: should be the frequency (in Hz) of the ciu clock. If this
62 * fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
63 specified, the default value of the fifo size is determined from the
66 * card-detect-delay: Delay in milli-seconds before detecting card after card
69 * data-addr: Override fifo address with value provided by DT. The default FIFO reg
72 to set fifo address in device tree.
74 * fifo-watermark-aligned: Data done irq is expected if data length is less than
75 watermark in PIO mode. But fifo watermark is requested to be aligned with data
76 length in some SoC so that TX/RX irq can be generated with data done irq. Add this
77 watermark quirk to mark this requirement and force fifo watermark setting
80 * vmmc-supply: The phandle to the regulator to use for vmmc. If this is
86 * dma-names: request names for generic DMA client binding. Must be "rx-tx".
91 - All the MSHC controller nodes should be represented in the aliases node using
100 compatible = "snps,dw-mshc";
102 clock-names = "biu", "ciu";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 data-addr = <0x200>;
108 fifo-watermark-aligned;
110 reset-names = "reset";
116 clock-frequency = <400000000>;
117 clock-freq-min-max = <400000 200000000>;
118 broken-cd;
119 fifo-depth = <0x80>;
120 card-detect-delay = <200>;
121 vmmc-supply = <&buck8>;
122 bus-width = <8>;
123 cap-mmc-highspeed;
124 cap-sd-highspeed;
130 clock-frequency = <400000000>;
131 clock-freq-min-max = <400000 200000000>;
132 broken-cd;
133 fifo-depth = <0x80>;
134 card-detect-delay = <200>;
135 vmmc-supply = <&buck8>;
136 bus-width = <8>;
137 cap-mmc-highspeed;
138 cap-sd-highspeed;
140 dma-names = "rx-tx";