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/Linux-v5.10/drivers/net/ethernet/intel/e1000/
De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/Linux-v5.10/drivers/net/ethernet/mscc/
Docelot_vsc7514.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
21 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
24 REG(ANA_ADVLEARN, 0x009000),
25 REG(ANA_VLANMASK, 0x009004),
26 REG(ANA_PORT_B_DOMAIN, 0x009008),
27 REG(ANA_ANAGEFIL, 0x00900c),
28 REG(ANA_ANEVENTS, 0x009010),
29 REG(ANA_STORMLIMIT_BURST, 0x009014),
30 REG(ANA_STORMLIMIT_CFG, 0x009018),
31 REG(ANA_ISOLATED_PORTS, 0x009028),
[all …]
Docelot_io.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset) in __ocelot_read_ix() argument
15 u16 target = reg >> TARGET_OFFSET; in __ocelot_read_ix()
20 regmap_read(ocelot->targets[target], in __ocelot_read_ix()
21 ocelot->map[target][reg & REG_MASK] + offset, &val); in __ocelot_read_ix()
26 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset) in __ocelot_write_ix() argument
28 u16 target = reg >> TARGET_OFFSET; in __ocelot_write_ix()
32 regmap_write(ocelot->targets[target], in __ocelot_write_ix()
33 ocelot->map[target][reg & REG_MASK] + offset, val); in __ocelot_write_ix()
37 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, in __ocelot_rmw_ix() argument
[all …]
/Linux-v5.10/drivers/net/dsa/ocelot/
Dseville_vsc9953.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/pcs-lynx.h>
23 REG(ANA_ADVLEARN, 0x00b500),
24 REG(ANA_VLANMASK, 0x00b504),
26 REG(ANA_ANAGEFIL, 0x00b50c),
27 REG(ANA_ANEVENTS, 0x00b510),
28 REG(ANA_STORMLIMIT_BURST, 0x00b514),
29 REG(ANA_STORMLIMIT_CFG, 0x00b518),
30 REG(ANA_ISOLATED_PORTS, 0x00b528),
31 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
[all …]
Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP Semiconductors
12 #include <linux/pcs-lynx.h>
22 REG(ANA_ADVLEARN, 0x0089a0),
23 REG(ANA_VLANMASK, 0x0089a4),
25 REG(ANA_ANAGEFIL, 0x0089ac),
26 REG(ANA_ANEVENTS, 0x0089b0),
27 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
28 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
29 REG(ANA_ISOLATED_PORTS, 0x0089c8),
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_translate_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/Linux-v5.10/drivers/gpio/
Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
27 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
30 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
33 unsigned int reg; in palmas_gpio_get() local
34 int gpio16 = (offset/8); in palmas_gpio_get()
36 offset %= 8; in palmas_gpio_get()
37 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
39 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
41 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
45 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
Dgpio-msic.c1 // SPDX-License-Identifier: GPL-2.0
18 /* the offset for the mapping of global gpio pin to irq */
52 * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
61 static int msic_gpio_to_ireg(unsigned offset) in msic_gpio_to_ireg() argument
63 if (offset >= MSIC_NUM_GPIO) in msic_gpio_to_ireg()
64 return -EINVAL; in msic_gpio_to_ireg()
66 if (offset < 8) in msic_gpio_to_ireg()
67 return INTEL_MSIC_GPIO0LV0CTLI - offset; in msic_gpio_to_ireg()
68 if (offset < 16) in msic_gpio_to_ireg()
69 return INTEL_MSIC_GPIO1LV0CTLI - offset + 8; in msic_gpio_to_ireg()
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Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
52 * @offset: the EIC controller's offset address of the PMIC.
53 * @reg: the array to cache the EIC registers.
61 u32 offset; member
62 u8 reg[CACHE_NR_REGS]; member
67 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
68 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
71 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
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Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
210 const enum aspeed_gpio_reg reg) in bank_reg() argument
212 switch (reg) { in bank_reg()
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
216 return gpio->base + bank->rdata_reg; in bank_reg()
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
[all …]
Dgpio-cs5535.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
61 unsigned int reg) in errata_outl() argument
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
69 * read-modify-write operation. in errata_outl()
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Dgpio-pcie-idio-24.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCIe-IDIO-24 family
15 * This driver supports the following ACCES devices: PCIe-IDIO-24,
16 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
58 * 23: Built-In Self-Test (BIST) Interrupt Active
73 * struct idio_24_gpio_reg - GPIO device registers structure
74 * @out0_7: Read: FET Outputs 0-7
75 * Write: FET Outputs 0-7
76 * @out8_15: Read: FET Outputs 8-15
77 * Write: FET Outputs 8-15
[all …]
Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
101 const enum aspeed_sgpio_reg reg) in bank_reg() argument
103 switch (reg) { in bank_reg()
105 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
107 return gpio->base + bank->rdata_reg; in bank_reg()
109 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
111 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_translate_dcn20.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_translate_dcn30.c27 * Pre-requisites: headers required by header of this unit
60 #undef REG
61 #define REG(reg_name)\ macro
72 uint32_t offset, in offset_to_id() argument
77 switch (offset) { in offset_to_id()
79 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
109 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
136 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_translate_dcn21.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
65 uint32_t offset, in offset_to_id() argument
70 switch (offset) { in offset_to_id()
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
106 case REG(DC_GPIO_HPD_A): in offset_to_id()
132 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
133 case REG(DC_GPIO_GENLK_A): in offset_to_id()
157 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/Linux-v5.10/net/netfilter/
Dnft_payload.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2009 Patrick McHardy <kaber@trash.net>
19 /* For layer 4 checksum field offset. */
33 veth->h_vlan_proto = skb->vlan_proto; in nft_payload_rebuild_vlan_hdr()
34 veth->h_vlan_TCI = htons(skb_vlan_tag_get(skb)); in nft_payload_rebuild_vlan_hdr()
35 veth->h_vlan_encapsulated_proto = skb->protocol; in nft_payload_rebuild_vlan_hdr()
42 nft_payload_copy_vlan(u32 *d, const struct sk_buff *skb, u8 offset, u8 len) in nft_payload_copy_vlan() argument
44 int mac_off = skb_mac_header(skb) - skb->data; in nft_payload_copy_vlan()
49 if ((skb->protocol == htons(ETH_P_8021AD) || in nft_payload_copy_vlan()
50 skb->protocol == htons(ETH_P_8021Q)) && in nft_payload_copy_vlan()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/
Dcgs_common.h32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
86 * @offset: register offset
90 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
93 * cgs_write_register() - Write an MMIO register
95 * @offset: register offset
98 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
102 * cgs_read_ind_register() - Read an indirect register
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/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dinit.c42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
74 init->execute ^= 0x02; in init_exec_inv()
80 if (exec) init->execute |= 0x04; in init_exec_force()
81 else init->execute &= 0xfb; in init_exec_force()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mpc.c33 #define REG(reg)\ macro
34 mpc30->mpc_regs->reg
37 mpc30->base.ctx
41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
98 MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode, in mpc3_set_out_rate_control()
99 MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1); in mpc3_set_out_rate_control()
165 struct dcn3_xfer_func_reg *reg) in mpc3_ogam_get_reg_field() argument
169 reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
170 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
171 reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
[all …]
/Linux-v5.10/drivers/net/dsa/mv88e6xxx/
Dglobal2_scratch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 /* Offset 0x1A: Scratch and Misc. Register */
15 static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg, in mv88e6xxx_g2_scratch_read() argument
22 reg << 8); in mv88e6xxx_g2_scratch_read()
35 static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg, in mv88e6xxx_g2_scratch_write() argument
38 u16 value = (reg << 8) | data; in mv88e6xxx_g2_scratch_write()
45 * mv88e6xxx_g2_scratch_gpio_get_bit - get a bit
48 * @offset: index of bit within the register
52 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_get_bit() argument
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit() local
[all …]
/Linux-v5.10/drivers/gpu/drm/vc4/
Dvc4_hdmi_regs.h34 * Transmit data, first byte is low byte of the 32-bit reg.
57 * 20-bit fields containing CTS values to be transmitted if
125 enum vc4_hdmi_regs reg; member
126 unsigned int offset; member
132 .reg = _base, \
133 .offset = _offset, \
136 #define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) argument
137 #define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) argument
138 #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset) argument
139 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) argument
[all …]
/Linux-v5.10/arch/mips/boot/dts/mti/
Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
33 reg = <0x0 0x08000000>;
36 cpu_intc: interrupt-controller {
[all …]

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