Lines Matching +full:reg +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-or-later
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
210 const enum aspeed_gpio_reg reg) in bank_reg() argument
212 switch (reg) { in bank_reg()
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
216 return gpio->base + bank->rdata_reg; in bank_reg()
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
230 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in bank_reg()
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in bank_reg()
234 return gpio->base + bank->tolerance_regs; in bank_reg()
236 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in bank_reg()
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in bank_reg()
251 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) in to_bank() argument
253 unsigned int bank = GPIO_BANK(offset); in to_bank()
261 return !(props->input || props->output); in is_bank_props_sentinel()
265 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
267 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
270 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
281 const struct aspeed_gpio_bank *bank = to_bank(offset); in have_gpio()
282 unsigned int group = GPIO_OFFSET(offset) / 8; in have_gpio()
284 return bank->names[group][0] != '\0' && in have_gpio()
285 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
290 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_input()
292 return !props || (props->input & GPIO_BIT(offset)); in have_input()
298 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) in have_output() argument
300 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_output()
302 return !props || (props->output & GPIO_BIT(offset)); in have_output()
311 u32 bit, reg; in aspeed_gpio_change_cmd_source() local
321 reg = ioread32(c1); in aspeed_gpio_change_cmd_source()
323 reg |= bit; in aspeed_gpio_change_cmd_source()
325 reg &= ~bit; in aspeed_gpio_change_cmd_source()
326 iowrite32(reg, c1); in aspeed_gpio_change_cmd_source()
329 reg = ioread32(c0); in aspeed_gpio_change_cmd_source()
331 reg |= bit; in aspeed_gpio_change_cmd_source()
333 reg &= ~bit; in aspeed_gpio_change_cmd_source()
334 iowrite32(reg, c0); in aspeed_gpio_change_cmd_source()
338 unsigned int offset) in aspeed_gpio_copro_request() argument
340 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_request()
342 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_request()
344 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_request()
346 if (!copro_ops->request_access) in aspeed_gpio_copro_request()
350 copro_ops->request_access(copro_data); in aspeed_gpio_copro_request()
353 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); in aspeed_gpio_copro_request()
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
362 unsigned int offset) in aspeed_gpio_copro_release() argument
364 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release()
366 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_release()
368 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_release()
370 if (!copro_ops->release_access) in aspeed_gpio_copro_release()
374 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, in aspeed_gpio_copro_release()
378 copro_ops->release_access(copro_data); in aspeed_gpio_copro_release()
381 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_get() argument
384 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get()
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
389 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, in __aspeed_gpio_set() argument
393 const struct aspeed_gpio_bank *bank = to_bank(offset); in __aspeed_gpio_set()
395 u32 reg; in __aspeed_gpio_set() local
398 reg = gpio->dcache[GPIO_BANK(offset)]; in __aspeed_gpio_set()
401 reg |= GPIO_BIT(offset); in __aspeed_gpio_set()
403 reg &= ~GPIO_BIT(offset); in __aspeed_gpio_set()
404 gpio->dcache[GPIO_BANK(offset)] = reg; in __aspeed_gpio_set()
406 iowrite32(reg, addr); in __aspeed_gpio_set()
409 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, in aspeed_gpio_set() argument
416 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
417 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set()
419 __aspeed_gpio_set(gc, offset, val); in aspeed_gpio_set()
422 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set()
423 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
426 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_dir_in() argument
429 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_in()
433 u32 reg; in aspeed_gpio_dir_in() local
435 if (!have_input(gpio, offset)) in aspeed_gpio_dir_in()
436 return -ENOTSUPP; in aspeed_gpio_dir_in()
438 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
440 reg = ioread32(addr); in aspeed_gpio_dir_in()
441 reg &= ~GPIO_BIT(offset); in aspeed_gpio_dir_in()
443 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_in()
444 iowrite32(reg, addr); in aspeed_gpio_dir_in()
446 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_in()
448 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
454 unsigned int offset, int val) in aspeed_gpio_dir_out() argument
457 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_out()
461 u32 reg; in aspeed_gpio_dir_out() local
463 if (!have_output(gpio, offset)) in aspeed_gpio_dir_out()
464 return -ENOTSUPP; in aspeed_gpio_dir_out()
466 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
468 reg = ioread32(addr); in aspeed_gpio_dir_out()
469 reg |= GPIO_BIT(offset); in aspeed_gpio_dir_out()
471 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_out()
472 __aspeed_gpio_set(gc, offset, val); in aspeed_gpio_dir_out()
473 iowrite32(reg, addr); in aspeed_gpio_dir_out()
476 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_out()
477 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
482 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_get_direction() argument
485 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get_direction()
489 if (!have_input(gpio, offset)) in aspeed_gpio_get_direction()
492 if (!have_output(gpio, offset)) in aspeed_gpio_get_direction()
495 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
499 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
507 u32 *bit, int *offset) in irqd_to_aspeed_gpio_data() argument
511 *offset = irqd_to_hwirq(d); in irqd_to_aspeed_gpio_data()
516 if (!have_irq(internal, *offset)) in irqd_to_aspeed_gpio_data()
517 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
520 *bank = to_bank(*offset); in irqd_to_aspeed_gpio_data()
521 *bit = GPIO_BIT(*offset); in irqd_to_aspeed_gpio_data()
532 int rc, offset; in aspeed_gpio_irq_ack() local
536 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_ack()
542 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
543 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_ack()
548 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_ack()
549 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
557 u32 reg, bit; in aspeed_gpio_irq_set_mask() local
559 int rc, offset; in aspeed_gpio_irq_set_mask() local
562 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_set_mask()
568 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
569 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_set_mask()
571 reg = ioread32(addr); in aspeed_gpio_irq_set_mask()
573 reg |= bit; in aspeed_gpio_irq_set_mask()
575 reg &= ~bit; in aspeed_gpio_irq_set_mask()
576 iowrite32(reg, addr); in aspeed_gpio_irq_set_mask()
579 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_set_mask()
580 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
598 u32 bit, reg; in aspeed_gpio_set_type() local
604 int rc, offset; in aspeed_gpio_set_type() local
607 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_set_type()
609 return -EINVAL; in aspeed_gpio_set_type()
629 return -EINVAL; in aspeed_gpio_set_type()
632 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
633 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set_type()
636 reg = ioread32(addr); in aspeed_gpio_set_type()
637 reg = (reg & ~bit) | type0; in aspeed_gpio_set_type()
638 iowrite32(reg, addr); in aspeed_gpio_set_type()
641 reg = ioread32(addr); in aspeed_gpio_set_type()
642 reg = (reg & ~bit) | type1; in aspeed_gpio_set_type()
643 iowrite32(reg, addr); in aspeed_gpio_set_type()
646 reg = ioread32(addr); in aspeed_gpio_set_type()
647 reg = (reg & ~bit) | type2; in aspeed_gpio_set_type()
648 iowrite32(reg, addr); in aspeed_gpio_set_type()
651 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set_type()
652 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
665 unsigned long reg; in aspeed_gpio_irq_handler() local
670 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
674 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_gpio_irq_handler()
676 for_each_set_bit(p, ®, 32) { in aspeed_gpio_irq_handler()
677 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
691 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
694 unsigned int offset; in aspeed_init_irq_valid_mask() local
695 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask()
698 for_each_clear_bit(offset, &input, 32) { in aspeed_init_irq_valid_mask()
699 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
701 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
712 unsigned int offset, bool enable) in aspeed_gpio_reset_tolerance() argument
720 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_gpio_reset_tolerance()
722 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
723 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_reset_tolerance()
728 val |= GPIO_BIT(offset); in aspeed_gpio_reset_tolerance()
730 val &= ~GPIO_BIT(offset); in aspeed_gpio_reset_tolerance()
735 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_reset_tolerance()
736 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
741 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) in aspeed_gpio_request() argument
743 if (!have_gpio(gpiochip_get_data(chip), offset)) in aspeed_gpio_request()
744 return -ENODEV; in aspeed_gpio_request()
746 return pinctrl_gpio_request(chip->base + offset); in aspeed_gpio_request()
749 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) in aspeed_gpio_free() argument
751 pinctrl_gpio_free(chip->base + offset); in aspeed_gpio_free()
761 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
763 return -ENOTSUPP; in usecs_to_cycles()
769 return -ERANGE; in usecs_to_cycles()
777 /* Call under gpio->lock */
779 unsigned int offset, unsigned int timer) in register_allocated_timer() argument
781 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
782 "Offset %d already allocated timer %d\n", in register_allocated_timer()
783 offset, gpio->offset_timer[offset])) in register_allocated_timer()
784 return -EINVAL; in register_allocated_timer()
786 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
788 return -EPERM; in register_allocated_timer()
790 gpio->offset_timer[offset] = timer; in register_allocated_timer()
791 gpio->timer_users[timer]++; in register_allocated_timer()
796 /* Call under gpio->lock */
798 unsigned int offset) in unregister_allocated_timer() argument
800 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
801 "No timer allocated to offset %d\n", offset)) in unregister_allocated_timer()
802 return -EINVAL; in unregister_allocated_timer()
804 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
806 gpio->offset_timer[offset])) in unregister_allocated_timer()
807 return -EINVAL; in unregister_allocated_timer()
809 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
810 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
815 /* Call under gpio->lock */
817 unsigned int offset) in timer_allocation_registered() argument
819 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
822 /* Call under gpio->lock */
823 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, in configure_timer() argument
826 const struct aspeed_gpio_bank *bank = to_bank(offset); in configure_timer()
827 const u32 mask = GPIO_BIT(offset); in configure_timer()
836 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); in configure_timer()
840 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); in configure_timer()
843 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, in enable_debounce() argument
852 if (!gpio->clk) in enable_debounce()
853 return -EINVAL; in enable_debounce()
857 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
858 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
862 spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
864 if (timer_allocation_registered(gpio, offset)) { in enable_debounce()
865 rc = unregister_allocated_timer(gpio, offset); in enable_debounce()
874 cycles = ioread32(gpio->base + debounce_timers[i]); in enable_debounce()
886 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
887 if (gpio->timer_users[j] == 0) in enable_debounce()
891 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
892 dev_warn(chip->parent, in enable_debounce()
896 rc = -EPERM; in enable_debounce()
899 * We already adjusted the accounting to remove @offset in enable_debounce()
901 * the hardware so @offset has timers disabled for in enable_debounce()
904 configure_timer(gpio, offset, 0); in enable_debounce()
910 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); in enable_debounce()
914 rc = -EINVAL; in enable_debounce()
918 register_allocated_timer(gpio, offset, i); in enable_debounce()
919 configure_timer(gpio, offset, i); in enable_debounce()
922 spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
927 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) in disable_debounce() argument
933 spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
935 rc = unregister_allocated_timer(gpio, offset); in disable_debounce()
937 configure_timer(gpio, offset, 0); in disable_debounce()
939 spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
944 static int set_debounce(struct gpio_chip *chip, unsigned int offset, in set_debounce() argument
949 if (!have_debounce(gpio, offset)) in set_debounce()
950 return -ENOTSUPP; in set_debounce()
953 return enable_debounce(chip, offset, usecs); in set_debounce()
955 return disable_debounce(chip, offset); in set_debounce()
958 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, in aspeed_gpio_set_config() argument
965 return set_debounce(chip, offset, arg); in aspeed_gpio_set_config()
969 return pinctrl_gpio_set_config(offset, config); in aspeed_gpio_set_config()
972 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
973 return -ENOTSUPP; in aspeed_gpio_set_config()
975 return aspeed_gpio_reset_tolerance(chip, offset, arg); in aspeed_gpio_set_config()
977 return -ENOTSUPP; in aspeed_gpio_set_config()
981 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
996 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
1000 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1001 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1002 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1009 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_grab_gpio() local
1010 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_grab_gpio()
1013 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1014 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
1015 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1016 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
1017 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
1018 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
1019 bindex = offset >> 3; in aspeed_gpio_copro_grab_gpio()
1021 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1024 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
1025 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
1028 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
1031 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
1036 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
1038 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
1040 *bit = GPIO_OFFSET(offset); in aspeed_gpio_copro_grab_gpio()
1042 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1048 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1055 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_release_gpio() local
1056 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release_gpio()
1059 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1060 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1062 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1063 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1064 bindex = offset >> 3; in aspeed_gpio_copro_release_gpio()
1066 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1069 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1070 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1073 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1076 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1080 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1095 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1100 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1106 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1112 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1132 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1133 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1134 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1146 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1148 return -ENOMEM; in aspeed_gpio_probe()
1150 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1151 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1152 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1154 spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1156 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1158 return -EINVAL; in aspeed_gpio_probe()
1160 gpio->clk = of_clk_get(pdev->dev.of_node, 0); in aspeed_gpio_probe()
1161 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1162 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1164 gpio->clk = NULL; in aspeed_gpio_probe()
1167 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1169 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1170 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1171 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1173 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1174 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1175 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1176 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1177 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1178 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1179 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1180 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1181 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1182 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1183 gpio->chip.base = -1; in aspeed_gpio_probe()
1186 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1187 gpio->dcache = devm_kcalloc(&pdev->dev, in aspeed_gpio_probe()
1189 if (!gpio->dcache) in aspeed_gpio_probe()
1190 return -ENOMEM; in aspeed_gpio_probe()
1199 gpio->dcache[i] = ioread32(addr); in aspeed_gpio_probe()
1211 gpio->irq = rc; in aspeed_gpio_probe()
1212 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1213 girq->chip = &gpio->irqc; in aspeed_gpio_probe()
1214 girq->chip->name = dev_name(&pdev->dev); in aspeed_gpio_probe()
1215 girq->chip->irq_ack = aspeed_gpio_irq_ack; in aspeed_gpio_probe()
1216 girq->chip->irq_mask = aspeed_gpio_irq_mask; in aspeed_gpio_probe()
1217 girq->chip->irq_unmask = aspeed_gpio_irq_unmask; in aspeed_gpio_probe()
1218 girq->chip->irq_set_type = aspeed_gpio_set_type; in aspeed_gpio_probe()
1219 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1220 girq->num_parents = 1; in aspeed_gpio_probe()
1221 girq->parents = devm_kcalloc(&pdev->dev, 1, in aspeed_gpio_probe()
1222 sizeof(*girq->parents), in aspeed_gpio_probe()
1224 if (!girq->parents) in aspeed_gpio_probe()
1225 return -ENOMEM; in aspeed_gpio_probe()
1226 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1227 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1228 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1229 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1232 gpio->offset_timer = in aspeed_gpio_probe()
1233 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1234 if (!gpio->offset_timer) in aspeed_gpio_probe()
1235 return -ENOMEM; in aspeed_gpio_probe()
1237 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()