Lines Matching +full:reg +full:- +full:offset
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/pcs-lynx.h>
23 REG(ANA_ADVLEARN, 0x00b500),
24 REG(ANA_VLANMASK, 0x00b504),
26 REG(ANA_ANAGEFIL, 0x00b50c),
27 REG(ANA_ANEVENTS, 0x00b510),
28 REG(ANA_STORMLIMIT_BURST, 0x00b514),
29 REG(ANA_STORMLIMIT_CFG, 0x00b518),
30 REG(ANA_ISOLATED_PORTS, 0x00b528),
31 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
32 REG(ANA_AUTOAGE, 0x00b530),
33 REG(ANA_MACTOPTIONS, 0x00b534),
34 REG(ANA_LEARNDISC, 0x00b538),
35 REG(ANA_AGENCTRL, 0x00b53c),
36 REG(ANA_MIRRORPORTS, 0x00b540),
37 REG(ANA_EMIRRORPORTS, 0x00b544),
38 REG(ANA_FLOODING, 0x00b548),
39 REG(ANA_FLOODING_IPMC, 0x00b54c),
40 REG(ANA_SFLOW_CFG, 0x00b550),
41 REG(ANA_PORT_MODE, 0x00b57c),
43 REG(ANA_PGID_PGID, 0x00b600),
44 REG(ANA_TABLES_ANMOVED, 0x00b4ac),
45 REG(ANA_TABLES_MACHDATA, 0x00b4b0),
46 REG(ANA_TABLES_MACLDATA, 0x00b4b4),
48 REG(ANA_TABLES_MACACCESS, 0x00b4b8),
49 REG(ANA_TABLES_MACTINDX, 0x00b4bc),
50 REG(ANA_TABLES_VLANACCESS, 0x00b4c0),
51 REG(ANA_TABLES_VLANTIDX, 0x00b4c4),
54 REG(ANA_TABLES_ENTRYLIM, 0x00b480),
77 REG(ANA_PORT_VLAN_CFG, 0x000000),
78 REG(ANA_PORT_DROP_CFG, 0x000004),
79 REG(ANA_PORT_QOS_CFG, 0x000008),
80 REG(ANA_PORT_VCAP_CFG, 0x00000c),
81 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010),
82 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c),
83 REG(ANA_PORT_PCP_DEI_MAP, 0x000020),
84 REG(ANA_PORT_CPU_FWD_CFG, 0x000060),
85 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064),
86 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068),
87 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c),
88 REG(ANA_PORT_PORT_CFG, 0x000070),
89 REG(ANA_PORT_POL_CFG, 0x000074),
94 REG(ANA_PFC_PFC_CFG, 0x00c000),
100 REG(ANA_AGGR_CFG, 0x00c600),
101 REG(ANA_CPUQ_CFG, 0x00c604),
103 REG(ANA_CPUQ_8021_CFG, 0x00c60c),
104 REG(ANA_DSCP_CFG, 0x00c64c),
105 REG(ANA_DSCP_REWR_CFG, 0x00c74c),
106 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c),
107 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac),
111 REG(ANA_DISCARD_CFG, 0x00c7d8),
112 REG(ANA_FID_CFG, 0x00c7dc),
113 REG(ANA_POL_PIR_CFG, 0x00a000),
114 REG(ANA_POL_CIR_CFG, 0x00a004),
115 REG(ANA_POL_MODE_CFG, 0x00a008),
116 REG(ANA_POL_PIR_STATE, 0x00a00c),
117 REG(ANA_POL_CIR_STATE, 0x00a010),
119 REG(ANA_POL_FLOWC, 0x00c280),
120 REG(ANA_POL_HYST, 0x00c2ec),
125 REG(QS_XTR_GRP_CFG, 0x000000),
126 REG(QS_XTR_RD, 0x000008),
127 REG(QS_XTR_FRM_PRUNING, 0x000010),
128 REG(QS_XTR_FLUSH, 0x000018),
129 REG(QS_XTR_DATA_PRESENT, 0x00001c),
130 REG(QS_XTR_CFG, 0x000020),
131 REG(QS_INJ_GRP_CFG, 0x000024),
132 REG(QS_INJ_WR, 0x00002c),
133 REG(QS_INJ_CTRL, 0x000034),
134 REG(QS_INJ_STATUS, 0x00003c),
135 REG(QS_INJ_ERR, 0x000040),
141 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
142 REG(VCAP_CORE_MV_CFG, 0x000004),
144 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
145 REG(VCAP_CACHE_MASK_DAT, 0x000108),
146 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
147 REG(VCAP_CACHE_CNT_DAT, 0x000308),
148 REG(VCAP_CACHE_TG_DAT, 0x000388),
150 REG(VCAP_CONST_VCAP_VER, 0x000398),
151 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
152 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
153 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
154 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
155 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
156 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
157 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
163 REG(QSYS_PORT_MODE, 0x003600),
164 REG(QSYS_SWITCH_PORT_MODE, 0x003630),
165 REG(QSYS_STAT_CNT_CFG, 0x00365c),
166 REG(QSYS_EEE_CFG, 0x003660),
167 REG(QSYS_EEE_THRES, 0x003688),
168 REG(QSYS_IGR_NO_SHARING, 0x00368c),
169 REG(QSYS_EGR_NO_SHARING, 0x003690),
170 REG(QSYS_SW_STATUS, 0x003694),
171 REG(QSYS_EXT_CPU_CFG, 0x0036c0),
173 REG(QSYS_CPU_GROUP_MAP, 0x0036c8),
187 REG(QSYS_RED_PROFILE, 0x003724),
188 REG(QSYS_RES_QOS_MODE, 0x003764),
189 REG(QSYS_RES_CFG, 0x004000),
190 REG(QSYS_RES_STAT, 0x004004),
191 REG(QSYS_EGR_DROP_MODE, 0x003768),
192 REG(QSYS_EQ_CTRL, 0x00376c),
203 REG(QSYS_CIR_CFG, 0x000000),
205 REG(QSYS_SE_CFG, 0x000008),
206 REG(QSYS_SE_DWRR_CFG, 0x00000c),
209 REG(QSYS_CIR_STATE, 0x000044),
212 REG(QSYS_HSCH_MISC_CFG, 0x003774),
237 REG(REW_PORT_VLAN_CFG, 0x000000),
238 REG(REW_TAG_CFG, 0x000004),
239 REG(REW_PORT_CFG, 0x000008),
240 REG(REW_DSCP_CFG, 0x00000c),
241 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
245 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610),
246 REG(REW_DSCP_REMAP_CFG, 0x000710),
253 REG(SYS_COUNT_RX_OCTETS, 0x000000),
254 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
255 REG(SYS_COUNT_RX_SHORTS, 0x000010),
256 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
257 REG(SYS_COUNT_RX_JABBERS, 0x000018),
258 REG(SYS_COUNT_RX_64, 0x000024),
259 REG(SYS_COUNT_RX_65_127, 0x000028),
260 REG(SYS_COUNT_RX_128_255, 0x00002c),
261 REG(SYS_COUNT_RX_256_1023, 0x000030),
262 REG(SYS_COUNT_RX_1024_1526, 0x000034),
263 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
264 REG(SYS_COUNT_RX_LONGS, 0x000048),
265 REG(SYS_COUNT_TX_OCTETS, 0x000100),
266 REG(SYS_COUNT_TX_COLLISION, 0x000110),
267 REG(SYS_COUNT_TX_DROPS, 0x000114),
268 REG(SYS_COUNT_TX_64, 0x00011c),
269 REG(SYS_COUNT_TX_65_127, 0x000120),
270 REG(SYS_COUNT_TX_128_511, 0x000124),
271 REG(SYS_COUNT_TX_512_1023, 0x000128),
272 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
273 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
274 REG(SYS_COUNT_TX_AGING, 0x000178),
275 REG(SYS_RESET_CFG, 0x000318),
277 REG(SYS_VLAN_ETYPE_CFG, 0x000320),
278 REG(SYS_PORT_MODE, 0x000324),
279 REG(SYS_FRONT_PORT_MODE, 0x000354),
280 REG(SYS_FRM_AGING, 0x00037c),
281 REG(SYS_STAT_CFG, 0x000380),
287 REG(SYS_PAUSE_CFG, 0x00044c),
288 REG(SYS_PAUSE_TOT_CFG, 0x000478),
289 REG(SYS_ATOP, 0x00047c),
290 REG(SYS_ATOP_TOT_CFG, 0x0004a8),
291 REG(SYS_MAC_FC_CFG, 0x0004ac),
292 REG(SYS_MMGT, 0x0004d4),
310 REG(GCB_SOFT_RST, 0x000008),
311 REG(GCB_MIIM_MII_STATUS, 0x0000ac),
312 REG(GCB_MIIM_MII_CMD, 0x0000b4),
313 REG(GCB_MIIM_MII_DATA, 0x0000b8),
317 REG(DEV_CLOCK_CFG, 0x0),
318 REG(DEV_PORT_MISC, 0x4),
320 REG(DEV_EEE_CFG, 0xc),
324 REG(DEV_MAC_ENA_CFG, 0x10),
325 REG(DEV_MAC_MODE_CFG, 0x14),
326 REG(DEV_MAC_MAXLEN_CFG, 0x18),
327 REG(DEV_MAC_TAGS_CFG, 0x1c),
328 REG(DEV_MAC_ADV_CHK_CFG, 0x20),
329 REG(DEV_MAC_IFG_CFG, 0x24),
330 REG(DEV_MAC_HDX_CFG, 0x28),
332 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30),
333 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34),
334 REG(DEV_MAC_STICKY, 0x38),
528 { .offset = 0x00, .name = "rx_octets", },
529 { .offset = 0x01, .name = "rx_unicast", },
530 { .offset = 0x02, .name = "rx_multicast", },
531 { .offset = 0x03, .name = "rx_broadcast", },
532 { .offset = 0x04, .name = "rx_shorts", },
533 { .offset = 0x05, .name = "rx_fragments", },
534 { .offset = 0x06, .name = "rx_jabbers", },
535 { .offset = 0x07, .name = "rx_crc_align_errs", },
536 { .offset = 0x08, .name = "rx_sym_errs", },
537 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
538 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
539 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
540 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
541 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
542 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
543 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
544 { .offset = 0x10, .name = "rx_pause", },
545 { .offset = 0x11, .name = "rx_control", },
546 { .offset = 0x12, .name = "rx_longs", },
547 { .offset = 0x13, .name = "rx_classified_drops", },
548 { .offset = 0x14, .name = "rx_red_prio_0", },
549 { .offset = 0x15, .name = "rx_red_prio_1", },
550 { .offset = 0x16, .name = "rx_red_prio_2", },
551 { .offset = 0x17, .name = "rx_red_prio_3", },
552 { .offset = 0x18, .name = "rx_red_prio_4", },
553 { .offset = 0x19, .name = "rx_red_prio_5", },
554 { .offset = 0x1A, .name = "rx_red_prio_6", },
555 { .offset = 0x1B, .name = "rx_red_prio_7", },
556 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
557 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
558 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
559 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
560 { .offset = 0x20, .name = "rx_yellow_prio_4", },
561 { .offset = 0x21, .name = "rx_yellow_prio_5", },
562 { .offset = 0x22, .name = "rx_yellow_prio_6", },
563 { .offset = 0x23, .name = "rx_yellow_prio_7", },
564 { .offset = 0x24, .name = "rx_green_prio_0", },
565 { .offset = 0x25, .name = "rx_green_prio_1", },
566 { .offset = 0x26, .name = "rx_green_prio_2", },
567 { .offset = 0x27, .name = "rx_green_prio_3", },
568 { .offset = 0x28, .name = "rx_green_prio_4", },
569 { .offset = 0x29, .name = "rx_green_prio_5", },
570 { .offset = 0x2A, .name = "rx_green_prio_6", },
571 { .offset = 0x2B, .name = "rx_green_prio_7", },
572 { .offset = 0x40, .name = "tx_octets", },
573 { .offset = 0x41, .name = "tx_unicast", },
574 { .offset = 0x42, .name = "tx_multicast", },
575 { .offset = 0x43, .name = "tx_broadcast", },
576 { .offset = 0x44, .name = "tx_collision", },
577 { .offset = 0x45, .name = "tx_drops", },
578 { .offset = 0x46, .name = "tx_pause", },
579 { .offset = 0x47, .name = "tx_frames_below_65_octets", },
580 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", },
581 { .offset = 0x49, .name = "tx_frames_128_255_octets", },
582 { .offset = 0x4A, .name = "tx_frames_256_511_octets", },
583 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", },
584 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", },
585 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", },
586 { .offset = 0x4E, .name = "tx_yellow_prio_0", },
587 { .offset = 0x4F, .name = "tx_yellow_prio_1", },
588 { .offset = 0x50, .name = "tx_yellow_prio_2", },
589 { .offset = 0x51, .name = "tx_yellow_prio_3", },
590 { .offset = 0x52, .name = "tx_yellow_prio_4", },
591 { .offset = 0x53, .name = "tx_yellow_prio_5", },
592 { .offset = 0x54, .name = "tx_yellow_prio_6", },
593 { .offset = 0x55, .name = "tx_yellow_prio_7", },
594 { .offset = 0x56, .name = "tx_green_prio_0", },
595 { .offset = 0x57, .name = "tx_green_prio_1", },
596 { .offset = 0x58, .name = "tx_green_prio_2", },
597 { .offset = 0x59, .name = "tx_green_prio_3", },
598 { .offset = 0x5A, .name = "tx_green_prio_4", },
599 { .offset = 0x5B, .name = "tx_green_prio_5", },
600 { .offset = 0x5C, .name = "tx_green_prio_6", },
601 { .offset = 0x5D, .name = "tx_green_prio_7", },
602 { .offset = 0x5E, .name = "tx_aged", },
603 { .offset = 0x80, .name = "drop_local", },
604 { .offset = 0x81, .name = "drop_tail", },
605 { .offset = 0x82, .name = "drop_yellow_prio_0", },
606 { .offset = 0x83, .name = "drop_yellow_prio_1", },
607 { .offset = 0x84, .name = "drop_yellow_prio_2", },
608 { .offset = 0x85, .name = "drop_yellow_prio_3", },
609 { .offset = 0x86, .name = "drop_yellow_prio_4", },
610 { .offset = 0x87, .name = "drop_yellow_prio_5", },
611 { .offset = 0x88, .name = "drop_yellow_prio_6", },
612 { .offset = 0x89, .name = "drop_yellow_prio_7", },
613 { .offset = 0x8A, .name = "drop_green_prio_0", },
614 { .offset = 0x8B, .name = "drop_green_prio_1", },
615 { .offset = 0x8C, .name = "drop_green_prio_2", },
616 { .offset = 0x8D, .name = "drop_green_prio_3", },
617 { .offset = 0x8E, .name = "drop_green_prio_4", },
618 { .offset = 0x8F, .name = "drop_green_prio_5", },
619 { .offset = 0x90, .name = "drop_green_prio_6", },
620 { .offset = 0x91, .name = "drop_green_prio_7", },
676 /* Layer-3 Information */
682 /* Layer-4 Information */
901 struct ocelot *ocelot = bus->priv; in vsc9953_mdio_write()
908 dev_err(ocelot->dev, "MDIO write: pending timeout\n"); in vsc9953_mdio_write()
925 struct ocelot *ocelot = bus->priv; in vsc9953_mdio_read()
932 dev_err(ocelot->dev, "MDIO read: pending timeout\n"); in vsc9953_mdio_read()
946 dev_err(ocelot->dev, "MDIO read: busy timeout\n"); in vsc9953_mdio_read()
965 /* soft-reset the switch core */ in vsc9953_reset()
971 dev_err(ocelot->dev, "timeout: switch core reset\n"); in vsc9953_reset()
983 dev_err(ocelot->dev, "timeout: switch sram init\n"); in vsc9953_reset()
997 struct ocelot_port *ocelot_port = ocelot->ports[port]; in vsc9953_phylink_validate()
1000 if (state->interface != PHY_INTERFACE_MODE_NA && in vsc9953_phylink_validate()
1001 state->interface != ocelot_port->phy_mode) { in vsc9953_phylink_validate()
1016 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { in vsc9953_phylink_validate()
1023 bitmap_and(state->advertising, state->advertising, mask, in vsc9953_phylink_validate()
1033 return -ENOTSUPP; in vsc9953_prevalidate_phy_mode()
1037 /* Not supported on internal to-CPU ports */ in vsc9953_prevalidate_phy_mode()
1039 return -ENOTSUPP; in vsc9953_prevalidate_phy_mode()
1042 return -ENOTSUPP; in vsc9953_prevalidate_phy_mode()
1048 * Bit 8-0: Value to be multiplied with unit
1070 struct device *dev = ocelot->dev; in vsc9953_mdio_bus_alloc()
1075 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, in vsc9953_mdio_bus_alloc()
1078 if (!felix->pcs) { in vsc9953_mdio_bus_alloc()
1080 return -ENOMEM; in vsc9953_mdio_bus_alloc()
1085 return -ENOMEM; in vsc9953_mdio_bus_alloc()
1087 bus->name = "VSC9953 internal MDIO bus"; in vsc9953_mdio_bus_alloc()
1088 bus->read = vsc9953_mdio_read; in vsc9953_mdio_bus_alloc()
1089 bus->write = vsc9953_mdio_write; in vsc9953_mdio_bus_alloc()
1090 bus->parent = dev; in vsc9953_mdio_bus_alloc()
1091 bus->priv = ocelot; in vsc9953_mdio_bus_alloc()
1092 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); in vsc9953_mdio_bus_alloc()
1101 felix->imdio = bus; in vsc9953_mdio_bus_alloc()
1103 for (port = 0; port < felix->info->num_ports; port++) { in vsc9953_mdio_bus_alloc()
1104 struct ocelot_port *ocelot_port = ocelot->ports[port]; in vsc9953_mdio_bus_alloc()
1109 if (dsa_is_unused_port(felix->ds, port)) in vsc9953_mdio_bus_alloc()
1112 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) in vsc9953_mdio_bus_alloc()
1115 pcs = mdio_device_create(felix->imdio, addr); in vsc9953_mdio_bus_alloc()
1125 felix->pcs[port] = lynx; in vsc9953_mdio_bus_alloc()
1138 for (port = 0; port < ocelot->num_phys_ports; port++) { in vsc9953_mdio_bus_free()
1139 struct lynx_pcs *pcs = felix->pcs[port]; in vsc9953_mdio_bus_free()
1144 mdio_device_free(pcs->mdio); in vsc9953_mdio_bus_free()
1147 mdiobus_unregister(felix->imdio); in vsc9953_mdio_bus_free()
1152 struct ocelot_port *ocelot_port = ocelot->ports[port]; in vsc9953_xmit_template_populate()
1153 u8 *template = ocelot_port->xmit_template; in vsc9953_xmit_template_populate()
1161 src = ocelot->num_phys_ports; in vsc9953_xmit_template_populate()
1204 err = -ENOMEM; in seville_probe()
1205 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); in seville_probe()
1211 ocelot = &felix->ocelot; in seville_probe()
1212 ocelot->dev = &pdev->dev; in seville_probe()
1213 ocelot->num_flooding_pgids = 1; in seville_probe()
1214 felix->info = &seville_info_vsc9953; in seville_probe()
1217 felix->switch_base = res->start; in seville_probe()
1221 err = -ENOMEM; in seville_probe()
1222 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); in seville_probe()
1226 ds->dev = &pdev->dev; in seville_probe()
1227 ds->num_ports = felix->info->num_ports; in seville_probe()
1228 ds->ops = &felix_switch_ops; in seville_probe()
1229 ds->priv = ocelot; in seville_probe()
1230 felix->ds = ds; in seville_probe()
1234 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); in seville_probe()
1254 dsa_unregister_switch(felix->ds); in seville_remove()
1256 kfree(felix->ds); in seville_remove()
1263 { .compatible = "mscc,vsc9953-switch" },