1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
21 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
24 	REG(ANA_ADVLEARN,				0x009000),
25 	REG(ANA_VLANMASK,				0x009004),
26 	REG(ANA_PORT_B_DOMAIN,				0x009008),
27 	REG(ANA_ANAGEFIL,				0x00900c),
28 	REG(ANA_ANEVENTS,				0x009010),
29 	REG(ANA_STORMLIMIT_BURST,			0x009014),
30 	REG(ANA_STORMLIMIT_CFG,				0x009018),
31 	REG(ANA_ISOLATED_PORTS,				0x009028),
32 	REG(ANA_COMMUNITY_PORTS,			0x00902c),
33 	REG(ANA_AUTOAGE,				0x009030),
34 	REG(ANA_MACTOPTIONS,				0x009034),
35 	REG(ANA_LEARNDISC,				0x009038),
36 	REG(ANA_AGENCTRL,				0x00903c),
37 	REG(ANA_MIRRORPORTS,				0x009040),
38 	REG(ANA_EMIRRORPORTS,				0x009044),
39 	REG(ANA_FLOODING,				0x009048),
40 	REG(ANA_FLOODING_IPMC,				0x00904c),
41 	REG(ANA_SFLOW_CFG,				0x009050),
42 	REG(ANA_PORT_MODE,				0x009080),
43 	REG(ANA_PGID_PGID,				0x008c00),
44 	REG(ANA_TABLES_ANMOVED,				0x008b30),
45 	REG(ANA_TABLES_MACHDATA,			0x008b34),
46 	REG(ANA_TABLES_MACLDATA,			0x008b38),
47 	REG(ANA_TABLES_MACACCESS,			0x008b3c),
48 	REG(ANA_TABLES_MACTINDX,			0x008b40),
49 	REG(ANA_TABLES_VLANACCESS,			0x008b44),
50 	REG(ANA_TABLES_VLANTIDX,			0x008b48),
51 	REG(ANA_TABLES_ISDXACCESS,			0x008b4c),
52 	REG(ANA_TABLES_ISDXTIDX,			0x008b50),
53 	REG(ANA_TABLES_ENTRYLIM,			0x008b00),
54 	REG(ANA_TABLES_PTP_ID_HIGH,			0x008b54),
55 	REG(ANA_TABLES_PTP_ID_LOW,			0x008b58),
56 	REG(ANA_MSTI_STATE,				0x008e00),
57 	REG(ANA_PORT_VLAN_CFG,				0x007000),
58 	REG(ANA_PORT_DROP_CFG,				0x007004),
59 	REG(ANA_PORT_QOS_CFG,				0x007008),
60 	REG(ANA_PORT_VCAP_CFG,				0x00700c),
61 	REG(ANA_PORT_VCAP_S1_KEY_CFG,			0x007010),
62 	REG(ANA_PORT_VCAP_S2_CFG,			0x00701c),
63 	REG(ANA_PORT_PCP_DEI_MAP,			0x007020),
64 	REG(ANA_PORT_CPU_FWD_CFG,			0x007060),
65 	REG(ANA_PORT_CPU_FWD_BPDU_CFG,			0x007064),
66 	REG(ANA_PORT_CPU_FWD_GARP_CFG,			0x007068),
67 	REG(ANA_PORT_CPU_FWD_CCM_CFG,			0x00706c),
68 	REG(ANA_PORT_PORT_CFG,				0x007070),
69 	REG(ANA_PORT_POL_CFG,				0x007074),
70 	REG(ANA_PORT_PTP_CFG,				0x007078),
71 	REG(ANA_PORT_PTP_DLY1_CFG,			0x00707c),
72 	REG(ANA_OAM_UPM_LM_CNT,				0x007c00),
73 	REG(ANA_PORT_PTP_DLY2_CFG,			0x007080),
74 	REG(ANA_PFC_PFC_CFG,				0x008800),
75 	REG(ANA_PFC_PFC_TIMER,				0x008804),
76 	REG(ANA_IPT_OAM_MEP_CFG,			0x008000),
77 	REG(ANA_IPT_IPT,				0x008004),
78 	REG(ANA_PPT_PPT,				0x008ac0),
79 	REG(ANA_FID_MAP_FID_MAP,			0x000000),
80 	REG(ANA_AGGR_CFG,				0x0090b4),
81 	REG(ANA_CPUQ_CFG,				0x0090b8),
82 	REG(ANA_CPUQ_CFG2,				0x0090bc),
83 	REG(ANA_CPUQ_8021_CFG,				0x0090c0),
84 	REG(ANA_DSCP_CFG,				0x009100),
85 	REG(ANA_DSCP_REWR_CFG,				0x009200),
86 	REG(ANA_VCAP_RNG_TYPE_CFG,			0x009240),
87 	REG(ANA_VCAP_RNG_VAL_CFG,			0x009260),
88 	REG(ANA_VRAP_CFG,				0x009280),
89 	REG(ANA_VRAP_HDR_DATA,				0x009284),
90 	REG(ANA_VRAP_HDR_MASK,				0x009288),
91 	REG(ANA_DISCARD_CFG,				0x00928c),
92 	REG(ANA_FID_CFG,				0x009290),
93 	REG(ANA_POL_PIR_CFG,				0x004000),
94 	REG(ANA_POL_CIR_CFG,				0x004004),
95 	REG(ANA_POL_MODE_CFG,				0x004008),
96 	REG(ANA_POL_PIR_STATE,				0x00400c),
97 	REG(ANA_POL_CIR_STATE,				0x004010),
98 	REG(ANA_POL_STATE,				0x004014),
99 	REG(ANA_POL_FLOWC,				0x008b80),
100 	REG(ANA_POL_HYST,				0x008bec),
101 	REG(ANA_POL_MISC_CFG,				0x008bf0),
105 	REG(QS_XTR_GRP_CFG,				0x000000),
106 	REG(QS_XTR_RD,					0x000008),
107 	REG(QS_XTR_FRM_PRUNING,				0x000010),
108 	REG(QS_XTR_FLUSH,				0x000018),
109 	REG(QS_XTR_DATA_PRESENT,			0x00001c),
110 	REG(QS_XTR_CFG,					0x000020),
111 	REG(QS_INJ_GRP_CFG,				0x000024),
112 	REG(QS_INJ_WR,					0x00002c),
113 	REG(QS_INJ_CTRL,				0x000034),
114 	REG(QS_INJ_STATUS,				0x00003c),
115 	REG(QS_INJ_ERR,					0x000040),
116 	REG(QS_INH_DBG,					0x000048),
120 	REG(QSYS_PORT_MODE,				0x011200),
121 	REG(QSYS_SWITCH_PORT_MODE,			0x011234),
122 	REG(QSYS_STAT_CNT_CFG,				0x011264),
123 	REG(QSYS_EEE_CFG,				0x011268),
124 	REG(QSYS_EEE_THRES,				0x011294),
125 	REG(QSYS_IGR_NO_SHARING,			0x011298),
126 	REG(QSYS_EGR_NO_SHARING,			0x01129c),
127 	REG(QSYS_SW_STATUS,				0x0112a0),
128 	REG(QSYS_EXT_CPU_CFG,				0x0112d0),
129 	REG(QSYS_PAD_CFG,				0x0112d4),
130 	REG(QSYS_CPU_GROUP_MAP,				0x0112d8),
131 	REG(QSYS_QMAP,					0x0112dc),
132 	REG(QSYS_ISDX_SGRP,				0x011400),
133 	REG(QSYS_TIMED_FRAME_ENTRY,			0x014000),
134 	REG(QSYS_TFRM_MISC,				0x011310),
135 	REG(QSYS_TFRM_PORT_DLY,				0x011314),
136 	REG(QSYS_TFRM_TIMER_CFG_1,			0x011318),
137 	REG(QSYS_TFRM_TIMER_CFG_2,			0x01131c),
138 	REG(QSYS_TFRM_TIMER_CFG_3,			0x011320),
139 	REG(QSYS_TFRM_TIMER_CFG_4,			0x011324),
140 	REG(QSYS_TFRM_TIMER_CFG_5,			0x011328),
141 	REG(QSYS_TFRM_TIMER_CFG_6,			0x01132c),
142 	REG(QSYS_TFRM_TIMER_CFG_7,			0x011330),
143 	REG(QSYS_TFRM_TIMER_CFG_8,			0x011334),
144 	REG(QSYS_RED_PROFILE,				0x011338),
145 	REG(QSYS_RES_QOS_MODE,				0x011378),
146 	REG(QSYS_RES_CFG,				0x012000),
147 	REG(QSYS_RES_STAT,				0x012004),
148 	REG(QSYS_EGR_DROP_MODE,				0x01137c),
149 	REG(QSYS_EQ_CTRL,				0x011380),
150 	REG(QSYS_EVENTS_CORE,				0x011384),
151 	REG(QSYS_CIR_CFG,				0x000000),
152 	REG(QSYS_EIR_CFG,				0x000004),
153 	REG(QSYS_SE_CFG,				0x000008),
154 	REG(QSYS_SE_DWRR_CFG,				0x00000c),
155 	REG(QSYS_SE_CONNECT,				0x00003c),
156 	REG(QSYS_SE_DLB_SENSE,				0x000040),
157 	REG(QSYS_CIR_STATE,				0x000044),
158 	REG(QSYS_EIR_STATE,				0x000048),
159 	REG(QSYS_SE_STATE,				0x00004c),
160 	REG(QSYS_HSCH_MISC_CFG,				0x011388),
164 	REG(REW_PORT_VLAN_CFG,				0x000000),
165 	REG(REW_TAG_CFG,				0x000004),
166 	REG(REW_PORT_CFG,				0x000008),
167 	REG(REW_DSCP_CFG,				0x00000c),
168 	REG(REW_PCP_DEI_QOS_MAP_CFG,			0x000010),
169 	REG(REW_PTP_CFG,				0x000050),
170 	REG(REW_PTP_DLY1_CFG,				0x000054),
171 	REG(REW_DSCP_REMAP_DP1_CFG,			0x000690),
172 	REG(REW_DSCP_REMAP_CFG,				0x000790),
173 	REG(REW_STAT_CFG,				0x000890),
174 	REG(REW_PPT,					0x000680),
178 	REG(SYS_COUNT_RX_OCTETS,			0x000000),
179 	REG(SYS_COUNT_RX_UNICAST,			0x000004),
180 	REG(SYS_COUNT_RX_MULTICAST,			0x000008),
181 	REG(SYS_COUNT_RX_BROADCAST,			0x00000c),
182 	REG(SYS_COUNT_RX_SHORTS,			0x000010),
183 	REG(SYS_COUNT_RX_FRAGMENTS,			0x000014),
184 	REG(SYS_COUNT_RX_JABBERS,			0x000018),
185 	REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,		0x00001c),
186 	REG(SYS_COUNT_RX_SYM_ERRS,			0x000020),
187 	REG(SYS_COUNT_RX_64,				0x000024),
188 	REG(SYS_COUNT_RX_65_127,			0x000028),
189 	REG(SYS_COUNT_RX_128_255,			0x00002c),
190 	REG(SYS_COUNT_RX_256_1023,			0x000030),
191 	REG(SYS_COUNT_RX_1024_1526,			0x000034),
192 	REG(SYS_COUNT_RX_1527_MAX,			0x000038),
193 	REG(SYS_COUNT_RX_PAUSE,				0x00003c),
194 	REG(SYS_COUNT_RX_CONTROL,			0x000040),
195 	REG(SYS_COUNT_RX_LONGS,				0x000044),
196 	REG(SYS_COUNT_RX_CLASSIFIED_DROPS,		0x000048),
197 	REG(SYS_COUNT_TX_OCTETS,			0x000100),
198 	REG(SYS_COUNT_TX_UNICAST,			0x000104),
199 	REG(SYS_COUNT_TX_MULTICAST,			0x000108),
200 	REG(SYS_COUNT_TX_BROADCAST,			0x00010c),
201 	REG(SYS_COUNT_TX_COLLISION,			0x000110),
202 	REG(SYS_COUNT_TX_DROPS,				0x000114),
203 	REG(SYS_COUNT_TX_PAUSE,				0x000118),
204 	REG(SYS_COUNT_TX_64,				0x00011c),
205 	REG(SYS_COUNT_TX_65_127,			0x000120),
206 	REG(SYS_COUNT_TX_128_511,			0x000124),
207 	REG(SYS_COUNT_TX_512_1023,			0x000128),
208 	REG(SYS_COUNT_TX_1024_1526,			0x00012c),
209 	REG(SYS_COUNT_TX_1527_MAX,			0x000130),
210 	REG(SYS_COUNT_TX_AGING,				0x000170),
211 	REG(SYS_RESET_CFG,				0x000508),
212 	REG(SYS_CMID,					0x00050c),
213 	REG(SYS_VLAN_ETYPE_CFG,				0x000510),
214 	REG(SYS_PORT_MODE,				0x000514),
215 	REG(SYS_FRONT_PORT_MODE,			0x000548),
216 	REG(SYS_FRM_AGING,				0x000574),
217 	REG(SYS_STAT_CFG,				0x000578),
218 	REG(SYS_SW_STATUS,				0x00057c),
219 	REG(SYS_MISC_CFG,				0x0005ac),
220 	REG(SYS_REW_MAC_HIGH_CFG,			0x0005b0),
221 	REG(SYS_REW_MAC_LOW_CFG,			0x0005dc),
222 	REG(SYS_CM_ADDR,				0x000500),
223 	REG(SYS_CM_DATA,				0x000504),
224 	REG(SYS_PAUSE_CFG,				0x000608),
225 	REG(SYS_PAUSE_TOT_CFG,				0x000638),
226 	REG(SYS_ATOP,					0x00063c),
227 	REG(SYS_ATOP_TOT_CFG,				0x00066c),
228 	REG(SYS_MAC_FC_CFG,				0x000670),
229 	REG(SYS_MMGT,					0x00069c),
230 	REG(SYS_MMGT_FAST,				0x0006a0),
231 	REG(SYS_EVENTS_DIF,				0x0006a4),
232 	REG(SYS_EVENTS_CORE,				0x0006b4),
233 	REG(SYS_CNT,					0x000000),
234 	REG(SYS_PTP_STATUS,				0x0006b8),
235 	REG(SYS_PTP_TXSTAMP,				0x0006bc),
236 	REG(SYS_PTP_NXT,				0x0006c0),
237 	REG(SYS_PTP_CFG,				0x0006c4),
242 	REG(VCAP_CORE_UPDATE_CTRL,			0x000000),
243 	REG(VCAP_CORE_MV_CFG,				0x000004),
245 	REG(VCAP_CACHE_ENTRY_DAT,			0x000008),
246 	REG(VCAP_CACHE_MASK_DAT,			0x000108),
247 	REG(VCAP_CACHE_ACTION_DAT,			0x000208),
248 	REG(VCAP_CACHE_CNT_DAT,				0x000308),
249 	REG(VCAP_CACHE_TG_DAT,				0x000388),
251 	REG(VCAP_CONST_VCAP_VER,			0x000398),
252 	REG(VCAP_CONST_ENTRY_WIDTH,			0x00039c),
253 	REG(VCAP_CONST_ENTRY_CNT,			0x0003a0),
254 	REG(VCAP_CONST_ENTRY_SWCNT,			0x0003a4),
255 	REG(VCAP_CONST_ENTRY_TG_WIDTH,			0x0003a8),
256 	REG(VCAP_CONST_ACTION_DEF_CNT,			0x0003ac),
257 	REG(VCAP_CONST_ACTION_WIDTH,			0x0003b0),
258 	REG(VCAP_CONST_CNT_WIDTH,			0x0003b4),
259 	REG(VCAP_CONST_CORE_CNT,			0x0003b8),
260 	REG(VCAP_CONST_IF_CNT,				0x0003bc),
264 	REG(PTP_PIN_CFG,				0x000000),
265 	REG(PTP_PIN_TOD_SEC_MSB,			0x000004),
266 	REG(PTP_PIN_TOD_SEC_LSB,			0x000008),
267 	REG(PTP_PIN_TOD_NSEC,				0x00000c),
268 	REG(PTP_PIN_WF_HIGH_PERIOD,			0x000014),
269 	REG(PTP_PIN_WF_LOW_PERIOD,			0x000018),
270 	REG(PTP_CFG_MISC,				0x0000a0),
271 	REG(PTP_CLK_CFG_ADJ_CFG,			0x0000a4),
272 	REG(PTP_CLK_CFG_ADJ_FREQ,			0x0000a8),
276 	REG(DEV_CLOCK_CFG,				0x0),
277 	REG(DEV_PORT_MISC,				0x4),
278 	REG(DEV_EVENTS,					0x8),
279 	REG(DEV_EEE_CFG,				0xc),
280 	REG(DEV_RX_PATH_DELAY,				0x10),
281 	REG(DEV_TX_PATH_DELAY,				0x14),
282 	REG(DEV_PTP_PREDICT_CFG,			0x18),
283 	REG(DEV_MAC_ENA_CFG,				0x1c),
284 	REG(DEV_MAC_MODE_CFG,				0x20),
285 	REG(DEV_MAC_MAXLEN_CFG,				0x24),
286 	REG(DEV_MAC_TAGS_CFG,				0x28),
287 	REG(DEV_MAC_ADV_CHK_CFG,			0x2c),
288 	REG(DEV_MAC_IFG_CFG,				0x30),
289 	REG(DEV_MAC_HDX_CFG,				0x34),
290 	REG(DEV_MAC_DBG_CFG,				0x38),
291 	REG(DEV_MAC_FC_MAC_LOW_CFG,			0x3c),
292 	REG(DEV_MAC_FC_MAC_HIGH_CFG,			0x40),
293 	REG(DEV_MAC_STICKY,				0x44),
294 	REG(PCS1G_CFG,					0x48),
295 	REG(PCS1G_MODE_CFG,				0x4c),
296 	REG(PCS1G_SD_CFG,				0x50),
297 	REG(PCS1G_ANEG_CFG,				0x54),
298 	REG(PCS1G_ANEG_NP_CFG,				0x58),
299 	REG(PCS1G_LB_CFG,				0x5c),
300 	REG(PCS1G_DBG_CFG,				0x60),
301 	REG(PCS1G_CDET_CFG,				0x64),
302 	REG(PCS1G_ANEG_STATUS,				0x68),
303 	REG(PCS1G_ANEG_NP_STATUS,			0x6c),
304 	REG(PCS1G_LINK_STATUS,				0x70),
305 	REG(PCS1G_LINK_DOWN_CNT,			0x74),
306 	REG(PCS1G_STICKY,				0x78),
307 	REG(PCS1G_DEBUG_STATUS,				0x7c),
308 	REG(PCS1G_LPI_CFG,				0x80),
309 	REG(PCS1G_LPI_WAKE_ERROR_CNT,			0x84),
310 	REG(PCS1G_LPI_STATUS,				0x88),
311 	REG(PCS1G_TSTPAT_MODE_CFG,			0x8c),
312 	REG(PCS1G_TSTPAT_STATUS,			0x90),
313 	REG(DEV_PCS_FX100_CFG,				0x94),
314 	REG(DEV_PCS_FX100_STATUS,			0x98),
389 	{ .name = "rx_octets", .offset = 0x00, },
390 	{ .name = "rx_unicast", .offset = 0x01, },
391 	{ .name = "rx_multicast", .offset = 0x02, },
392 	{ .name = "rx_broadcast", .offset = 0x03, },
393 	{ .name = "rx_shorts", .offset = 0x04, },
394 	{ .name = "rx_fragments", .offset = 0x05, },
395 	{ .name = "rx_jabbers", .offset = 0x06, },
396 	{ .name = "rx_crc_align_errs", .offset = 0x07, },
397 	{ .name = "rx_sym_errs", .offset = 0x08, },
398 	{ .name = "rx_frames_below_65_octets", .offset = 0x09, },
399 	{ .name = "rx_frames_65_to_127_octets", .offset = 0x0A, },
400 	{ .name = "rx_frames_128_to_255_octets", .offset = 0x0B, },
401 	{ .name = "rx_frames_256_to_511_octets", .offset = 0x0C, },
402 	{ .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, },
403 	{ .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, },
404 	{ .name = "rx_frames_over_1526_octets", .offset = 0x0F, },
405 	{ .name = "rx_pause", .offset = 0x10, },
406 	{ .name = "rx_control", .offset = 0x11, },
407 	{ .name = "rx_longs", .offset = 0x12, },
408 	{ .name = "rx_classified_drops", .offset = 0x13, },
409 	{ .name = "rx_red_prio_0", .offset = 0x14, },
410 	{ .name = "rx_red_prio_1", .offset = 0x15, },
411 	{ .name = "rx_red_prio_2", .offset = 0x16, },
412 	{ .name = "rx_red_prio_3", .offset = 0x17, },
413 	{ .name = "rx_red_prio_4", .offset = 0x18, },
414 	{ .name = "rx_red_prio_5", .offset = 0x19, },
415 	{ .name = "rx_red_prio_6", .offset = 0x1A, },
416 	{ .name = "rx_red_prio_7", .offset = 0x1B, },
417 	{ .name = "rx_yellow_prio_0", .offset = 0x1C, },
418 	{ .name = "rx_yellow_prio_1", .offset = 0x1D, },
419 	{ .name = "rx_yellow_prio_2", .offset = 0x1E, },
420 	{ .name = "rx_yellow_prio_3", .offset = 0x1F, },
421 	{ .name = "rx_yellow_prio_4", .offset = 0x20, },
422 	{ .name = "rx_yellow_prio_5", .offset = 0x21, },
423 	{ .name = "rx_yellow_prio_6", .offset = 0x22, },
424 	{ .name = "rx_yellow_prio_7", .offset = 0x23, },
425 	{ .name = "rx_green_prio_0", .offset = 0x24, },
426 	{ .name = "rx_green_prio_1", .offset = 0x25, },
427 	{ .name = "rx_green_prio_2", .offset = 0x26, },
428 	{ .name = "rx_green_prio_3", .offset = 0x27, },
429 	{ .name = "rx_green_prio_4", .offset = 0x28, },
430 	{ .name = "rx_green_prio_5", .offset = 0x29, },
431 	{ .name = "rx_green_prio_6", .offset = 0x2A, },
432 	{ .name = "rx_green_prio_7", .offset = 0x2B, },
433 	{ .name = "tx_octets", .offset = 0x40, },
434 	{ .name = "tx_unicast", .offset = 0x41, },
435 	{ .name = "tx_multicast", .offset = 0x42, },
436 	{ .name = "tx_broadcast", .offset = 0x43, },
437 	{ .name = "tx_collision", .offset = 0x44, },
438 	{ .name = "tx_drops", .offset = 0x45, },
439 	{ .name = "tx_pause", .offset = 0x46, },
440 	{ .name = "tx_frames_below_65_octets", .offset = 0x47, },
441 	{ .name = "tx_frames_65_to_127_octets", .offset = 0x48, },
442 	{ .name = "tx_frames_128_255_octets", .offset = 0x49, },
443 	{ .name = "tx_frames_256_511_octets", .offset = 0x4A, },
444 	{ .name = "tx_frames_512_1023_octets", .offset = 0x4B, },
445 	{ .name = "tx_frames_1024_1526_octets", .offset = 0x4C, },
446 	{ .name = "tx_frames_over_1526_octets", .offset = 0x4D, },
447 	{ .name = "tx_yellow_prio_0", .offset = 0x4E, },
448 	{ .name = "tx_yellow_prio_1", .offset = 0x4F, },
449 	{ .name = "tx_yellow_prio_2", .offset = 0x50, },
450 	{ .name = "tx_yellow_prio_3", .offset = 0x51, },
451 	{ .name = "tx_yellow_prio_4", .offset = 0x52, },
452 	{ .name = "tx_yellow_prio_5", .offset = 0x53, },
453 	{ .name = "tx_yellow_prio_6", .offset = 0x54, },
454 	{ .name = "tx_yellow_prio_7", .offset = 0x55, },
455 	{ .name = "tx_green_prio_0", .offset = 0x56, },
456 	{ .name = "tx_green_prio_1", .offset = 0x57, },
457 	{ .name = "tx_green_prio_2", .offset = 0x58, },
458 	{ .name = "tx_green_prio_3", .offset = 0x59, },
459 	{ .name = "tx_green_prio_4", .offset = 0x5A, },
460 	{ .name = "tx_green_prio_5", .offset = 0x5B, },
461 	{ .name = "tx_green_prio_6", .offset = 0x5C, },
462 	{ .name = "tx_green_prio_7", .offset = 0x5D, },
463 	{ .name = "tx_aged", .offset = 0x5E, },
464 	{ .name = "drop_local", .offset = 0x80, },
465 	{ .name = "drop_tail", .offset = 0x81, },
466 	{ .name = "drop_yellow_prio_0", .offset = 0x82, },
467 	{ .name = "drop_yellow_prio_1", .offset = 0x83, },
468 	{ .name = "drop_yellow_prio_2", .offset = 0x84, },
469 	{ .name = "drop_yellow_prio_3", .offset = 0x85, },
470 	{ .name = "drop_yellow_prio_4", .offset = 0x86, },
471 	{ .name = "drop_yellow_prio_5", .offset = 0x87, },
472 	{ .name = "drop_yellow_prio_6", .offset = 0x88, },
473 	{ .name = "drop_yellow_prio_7", .offset = 0x89, },
474 	{ .name = "drop_green_prio_0", .offset = 0x8A, },
475 	{ .name = "drop_green_prio_1", .offset = 0x8B, },
476 	{ .name = "drop_green_prio_2", .offset = 0x8C, },
477 	{ .name = "drop_green_prio_3", .offset = 0x8D, },
478 	{ .name = "drop_green_prio_4", .offset = 0x8E, },
479 	{ .name = "drop_green_prio_5", .offset = 0x8F, },
480 	{ .name = "drop_green_prio_6", .offset = 0x90, },
481 	{ .name = "drop_green_prio_7", .offset = 0x91, },
489 	regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,  in ocelot_pll5_init()
492 	regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,  in ocelot_pll5_init()
504 	regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,  in ocelot_pll5_init()
517 	ocelot->map = ocelot_regmap;  in ocelot_chip_init()
518 	ocelot->stats_layout = ocelot_stats_layout;  in ocelot_chip_init()
519 	ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);  in ocelot_chip_init()
520 	ocelot->shared_queue_sz = 224 * 1024;  in ocelot_chip_init()
521 	ocelot->num_mact_rows = 1024;  in ocelot_chip_init()
522 	ocelot->ops = ops;  in ocelot_chip_init()
530 	eth_random_addr(ocelot->base_mac);  in ocelot_chip_init()
531 	ocelot->base_mac[5] &= 0xf0;  in ocelot_chip_init()
547 	info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;  in ocelot_parse_ifh()
549 	info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32);  in ocelot_parse_ifh()
551 	info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4);  in ocelot_parse_ifh()
553 	info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16,  1);  in ocelot_parse_ifh()
554 	info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0,  12);  in ocelot_parse_ifh()
568 			return -EIO;  in ocelot_rx_frame_word()
577 		return -EIO;  in ocelot_rx_frame_word()
642 		ocelot_port = ocelot->ports[info.port];  in ocelot_xtr_irq_handler()
645 		dev = priv->dev;  in ocelot_xtr_irq_handler()
651 			err = -ENOMEM;  in ocelot_xtr_irq_handler()
654 		buf_len = info.len - ETH_FCS_LEN;  in ocelot_xtr_irq_handler()
667 		len -= ETH_FCS_LEN - sz;  in ocelot_xtr_irq_handler()
669 		if (unlikely(dev->features & NETIF_F_RXFCS)) {  in ocelot_xtr_irq_handler()
679 		if (ocelot->ptp) {  in ocelot_xtr_irq_handler()
680 			ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);  in ocelot_xtr_irq_handler()
684 				full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |  in ocelot_xtr_irq_handler()
692 			shhwtstamps->hwtstamp = full_ts_in_ns;  in ocelot_xtr_irq_handler()
698 		if (ocelot->bridge_mask & BIT(info.port))  in ocelot_xtr_irq_handler()
699 			skb->offload_fwd_mark = 1;  in ocelot_xtr_irq_handler()
701 		skb->protocol = eth_type_trans(skb, dev);  in ocelot_xtr_irq_handler()
704 		dev->stats.rx_bytes += len;  in ocelot_xtr_irq_handler()
705 		dev->stats.rx_packets++;  in ocelot_xtr_irq_handler()
725 	{ .compatible = "mscc,vsc7514-switch" },
735 	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);  in ocelot_reset()
736 	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);  in ocelot_reset()
740 		regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],  in ocelot_reset()
742 	} while (val && --retries);  in ocelot_reset()
745 		return -ETIMEDOUT;  in ocelot_reset()
747 	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);  in ocelot_reset()
748 	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);  in ocelot_reset()
755  * Bit 7-0: Value to be multiplied with unit
827 	/* Layer-3 Information */
833 	/* Layer-4 Information */
1043 	for (port = 0; port < ocelot->num_phys_ports; port++) {  in mscc_ocelot_release_ports()
1047 		ocelot_port = ocelot->ports[port];  in mscc_ocelot_release_ports()
1056 		unregister_netdev(priv->dev);  in mscc_ocelot_release_ports()
1057 		free_netdev(priv->dev);  in mscc_ocelot_release_ports()
1068 	ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,  in mscc_ocelot_init_ports()
1070 	if (!ocelot->ports)  in mscc_ocelot_init_ports()
1071 		return -ENOMEM;  in mscc_ocelot_init_ports()
1085 		if (of_property_read_u32(portnp, "reg", &port))  in mscc_ocelot_init_ports()
1096 		phy_node = of_parse_phandle(portnp, "phy-handle", 0);  in mscc_ocelot_init_ports()
1111 		ocelot_port = ocelot->ports[port];  in mscc_ocelot_init_ports()
1117 		ocelot_port->phy_mode = phy_mode;  in mscc_ocelot_init_ports()
1119 		switch (ocelot_port->phy_mode) {  in mscc_ocelot_init_ports()
1134 			dev_err(ocelot->dev,  in mscc_ocelot_init_ports()
1138 			return -EINVAL;  in mscc_ocelot_init_ports()
1141 		serdes = devm_of_phy_get(ocelot->dev, portnp, NULL);  in mscc_ocelot_init_ports()
1144 			if (err == -EPROBE_DEFER)  in mscc_ocelot_init_ports()
1145 				dev_dbg(ocelot->dev, "deferring probe\n");  in mscc_ocelot_init_ports()
1147 				dev_err(ocelot->dev,  in mscc_ocelot_init_ports()
1155 		priv->serdes = serdes;  in mscc_ocelot_init_ports()
1163 	struct device_node *np = pdev->dev.of_node;  in mscc_ocelot_probe()
1186 	if (!np && !pdev->dev.platform_data)  in mscc_ocelot_probe()
1187 		return -ENODEV;  in mscc_ocelot_probe()
1189 	ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);  in mscc_ocelot_probe()
1191 		return -ENOMEM;  in mscc_ocelot_probe()
1194 	ocelot->dev = &pdev->dev;  in mscc_ocelot_probe()
1206 				ocelot->targets[io_target[i].id] = NULL;  in mscc_ocelot_probe()
1212 		ocelot->targets[io_target[i].id] = target;  in mscc_ocelot_probe()
1215 	hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");  in mscc_ocelot_probe()
1217 		dev_err(&pdev->dev, "missing hsio syscon\n");  in mscc_ocelot_probe()
1221 	ocelot->targets[HSIO] = hsio;  in mscc_ocelot_probe()
1229 		return -ENODEV;  in mscc_ocelot_probe()
1231 	err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL,  in mscc_ocelot_probe()
1238 	if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) {  in mscc_ocelot_probe()
1239 		err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL,  in mscc_ocelot_probe()
1247 		ocelot->ptp = 1;  in mscc_ocelot_probe()
1250 	ports = of_get_child_by_name(np, "ethernet-ports");  in mscc_ocelot_probe()
1252 		dev_err(ocelot->dev, "no ethernet-ports child node found\n");  in mscc_ocelot_probe()
1253 		return -ENODEV;  in mscc_ocelot_probe()
1256 	ocelot->num_phys_ports = of_get_child_count(ports);  in mscc_ocelot_probe()
1257 	ocelot->num_flooding_pgids = 1;  in mscc_ocelot_probe()
1259 	ocelot->vcap = vsc7514_vcap_props;  in mscc_ocelot_probe()
1260 	ocelot->inj_prefix = OCELOT_TAG_PREFIX_NONE;  in mscc_ocelot_probe()
1261 	ocelot->xtr_prefix = OCELOT_TAG_PREFIX_NONE;  in mscc_ocelot_probe()
1262 	ocelot->npi = -1;  in mscc_ocelot_probe()
1272 	if (ocelot->ptp) {  in mscc_ocelot_probe()
1275 			dev_err(ocelot->dev,  in mscc_ocelot_probe()
1277 			ocelot->ptp = 0;  in mscc_ocelot_probe()
1285 	dev_info(&pdev->dev, "Ocelot switch probed\n");  in mscc_ocelot_probe()
1310 		.name = "ocelot-switch",