1 // SPDX-License-Identifier: GPL-2.0-or-later
14 /* Offset 0x1A: Scratch and Misc. Register */
15 static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg,  in mv88e6xxx_g2_scratch_read()  argument
22 				 reg << 8);  in mv88e6xxx_g2_scratch_read()
35 static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg,  in mv88e6xxx_g2_scratch_write()  argument
38 	u16 value = (reg << 8) | data;  in mv88e6xxx_g2_scratch_write()
45  * mv88e6xxx_g2_scratch_gpio_get_bit - get a bit
48  * @offset: index of bit within the register
52 					int base_reg, unsigned int offset,  in mv88e6xxx_g2_scratch_get_bit()  argument
55 	int reg = base_reg + (offset / 8);  in mv88e6xxx_g2_scratch_get_bit()  local
56 	u8 mask = (1 << (offset & 0x7));  in mv88e6xxx_g2_scratch_get_bit()
60 	err = mv88e6xxx_g2_scratch_read(chip, reg, &val);  in mv88e6xxx_g2_scratch_get_bit()
70  * mv88e6xxx_g2_scratch_gpio_set_bit - set (or clear) a bit
73  * @offset: index of bit within the register
79 					int base_reg, unsigned int offset,  in mv88e6xxx_g2_scratch_set_bit()  argument
82 	int reg = base_reg + (offset / 8);  in mv88e6xxx_g2_scratch_set_bit()  local
83 	u8 mask = (1 << (offset & 0x7));  in mv88e6xxx_g2_scratch_set_bit()
87 	err = mv88e6xxx_g2_scratch_read(chip, reg, &val);  in mv88e6xxx_g2_scratch_set_bit()
96 	return mv88e6xxx_g2_scratch_write(chip, reg, val);  in mv88e6xxx_g2_scratch_set_bit()
100  * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
122  * mv88e6352_g2_scratch_gpio_set_data - set data on gpio pin
131 	int offset = (pin / 8);  in mv88e6352_g2_scratch_gpio_set_data()  local
132 	int reg;  in mv88e6352_g2_scratch_gpio_set_data()  local
134 	reg = MV88E6352_G2_SCRATCH_GPIO_DATA0 + offset;  in mv88e6352_g2_scratch_gpio_set_data()
137 		chip->gpio_data[offset] |= mask;  in mv88e6352_g2_scratch_gpio_set_data()
139 		chip->gpio_data[offset] &= ~mask;  in mv88e6352_g2_scratch_gpio_set_data()
141 	return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]);  in mv88e6352_g2_scratch_gpio_set_data()
145  * mv88e6352_g2_scratch_gpio_get_dir - get direction of gpio pin
167  * mv88e6352_g2_scratch_gpio_set_dir - set direction of gpio pin
184  * mv88e6352_g2_scratch_gpio_get_pctl - get pin control setting
194 	int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);  in mv88e6352_g2_scratch_gpio_get_pctl()  local
195 	int offset = (pin & 0x1) ? 4 : 0;  in mv88e6352_g2_scratch_gpio_get_pctl()  local
196 	u8 mask = (0x7 << offset);  in mv88e6352_g2_scratch_gpio_get_pctl()
200 	err = mv88e6xxx_g2_scratch_read(chip, reg, &val);  in mv88e6352_g2_scratch_gpio_get_pctl()
204 	*func = (val & mask) >> offset;  in mv88e6352_g2_scratch_gpio_get_pctl()
210  * mv88e6352_g2_scratch_gpio_set_pctl - set pin control setting
218 	int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);  in mv88e6352_g2_scratch_gpio_set_pctl()  local
219 	int offset = (pin & 0x1) ? 4 : 0;  in mv88e6352_g2_scratch_gpio_set_pctl()  local
220 	u8 mask = (0x7 << offset);  in mv88e6352_g2_scratch_gpio_set_pctl()
224 	err = mv88e6xxx_g2_scratch_read(chip, reg, &val);  in mv88e6352_g2_scratch_gpio_set_pctl()
228 	val = (val & ~mask) | ((func & mask) << offset);  in mv88e6352_g2_scratch_gpio_set_pctl()
230 	return mv88e6xxx_g2_scratch_write(chip, reg, val);  in mv88e6352_g2_scratch_gpio_set_pctl()
243  * mv88e6xxx_g2_gpio_set_smi - set gpio muxing for external smi
269 		return -EBUSY;  in mv88e6xxx_g2_scratch_gpio_set_smi()