/Linux-v5.10/arch/mips/bcm63xx/ |
D | clk.c | 33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked() 34 clk->set(clk, 1); in clk_enable_unlocked() 39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked() 40 clk->set(clk, 0); in clk_disable_unlocked() 43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument 48 if (enable) in bcm_hwclock_set() 49 reg |= mask; in bcm_hwclock_set() 51 reg &= ~mask; in bcm_hwclock_set() 58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument 60 u32 mask; in enet_misc_set() local [all …]
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/Linux-v5.10/include/linux/iio/common/ |
D | st_sensors.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright 2012-2013 STMicroelectronics Inc. 49 #define ST_SENSORS_LSM_CHANNELS(device_type, mask, index, mod, \ argument 54 .info_mask_separate = mask, \ 62 .shift = sbits - rbits, \ 83 u8 mask; member 89 u8 mask; member 96 u8 mask; member 108 u8 mask; member 118 * struct st_sensor_bdu - ST sensor device block data update [all …]
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/Linux-v5.10/include/linux/ |
D | via-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved. 4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net> 99 void viafb_irq_enable(u32 mask); 100 void viafb_irq_disable(u32 mask); 117 #define VDE_I_HQV1EN 0x00000800 /* Second HQV engine enable */ 122 #define VDE_I_DVISNSEN 0x00010000 /* DVI sense enable */ 123 #define VDE_I_VSYNC2EN 0x00020000 /* Sec Disp VSYNC enable */ 124 #define VDE_I_MCCFIEN 0x00040000 /* MC comp frame int mask enable */ [all …]
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D | pxa2xx_ssp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * This driver supports the following PXA CPU/SSP ports:- 50 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */ 51 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 52 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */ 57 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */ 58 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ 63 #define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */ 64 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */ 65 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/hwmon/ |
D | max6697.txt | 4 - compatible: 16 - reg: I2C address 20 - smbus-timeout-disable 23 - extended-range-enable 24 Only valid for MAX6581. Set to enable extended temperature range. 26 - beta-compensation-enable 27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on 30 - alert-mask 31 Alert bit mask. Alert disabled for bits set. 34 - over-temperature-mask [all …]
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/Linux-v5.10/drivers/media/rc/ |
D | rc-loopback.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Loopback driver for rc-core, 8 * which is useful for (scripted) debugging of rc-core without 16 #include <media/rc-core.h> 18 #define DRIVER_NAME "rc-loopback" 39 static int loop_set_tx_mask(struct rc_dev *dev, u32 mask) in loop_set_tx_mask() argument 41 struct loopback_dev *lodev = dev->priv; in loop_set_tx_mask() 43 if ((mask & (RXMASK_REGULAR | RXMASK_LEARNING)) != mask) { in loop_set_tx_mask() 44 dprintk("invalid tx mask: %u\n", mask); in loop_set_tx_mask() 45 return -EINVAL; in loop_set_tx_mask() [all …]
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D | ite-cir.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 9 #define ITE_DRIVER_NAME "ite-cir" 64 /* duty cycle, 0-100 */ 67 /* hw-specific operation function pointers; most of these must be 73 /* enable rx */ 86 /* enable tx FIFO space available interrupt */ 137 /* low-speed carrier frequency limits (Hz) */ 141 /* high-speed carrier frequency limits (Hz) */ 153 * n in RDCR produces a tolerance of +/- n * 6.25% around the center 158 * frequency A = (H - L) / (H + L). We can use this in order to honor the [all …]
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/Linux-v5.10/drivers/iio/imu/inv_mpu6050/ |
D | inv_mpu_trigger.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 unsigned int mask; in inv_scan_query_mpu6050() local 14 st->chip_config.gyro_fifo_enable = in inv_scan_query_mpu6050() 16 indio_dev->active_scan_mask) || in inv_scan_query_mpu6050() 18 indio_dev->active_scan_mask) || in inv_scan_query_mpu6050() 20 indio_dev->active_scan_mask); in inv_scan_query_mpu6050() 22 st->chip_config.accl_fifo_enable = in inv_scan_query_mpu6050() 24 indio_dev->active_scan_mask) || in inv_scan_query_mpu6050() 26 indio_dev->active_scan_mask) || in inv_scan_query_mpu6050() 28 indio_dev->active_scan_mask); in inv_scan_query_mpu6050() [all …]
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/Linux-v5.10/drivers/fpga/ |
D | altera-fpga2sdram.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved. 23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed. 26 #include <linux/fpga/fpga-bridge.h> 53 int mask; member 58 struct alt_fpga2sdram_data *priv = bridge->priv; in alt_fpga2sdram_enable_show() 61 regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value); in alt_fpga2sdram_enable_show() 63 return (value & priv->mask) == priv->mask; in alt_fpga2sdram_enable_show() 67 bool enable) in _alt_fpga2sdram_enable_set() argument 69 return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, in _alt_fpga2sdram_enable_set() [all …]
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/Linux-v5.10/drivers/net/wireless/ath/ath5k/ |
D | reg.h | 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> 28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf 30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf 33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal 42 * AR5210-Specific TXDP registers 46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ 47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ 53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ [all …]
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/Linux-v5.10/arch/arm64/boot/dts/hisilicon/ |
D | poplar-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. 8 #include <dt-bindings/pinctrl/hisi.h> 10 /* value, enable bits, disable bits, mask */ 11 #define PINCTRL_PULLDOWN(value, enable, disable, mask) \ argument 12 (value << 13) (enable << 13) (disable << 13) (mask << 13) 13 #define PINCTRL_PULLUP(value, enable, disable, mask) \ argument 14 (value << 12) (enable << 12) (disable << 12) (mask << 12) 15 #define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) argument 16 #define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) argument [all …]
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/Linux-v5.10/include/linux/mfd/ |
D | rohm-generic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 33 * struct rohm_dvs_config - dynamic voltage scaling register descriptions 35 * @level_map: bitmap representing supported run-levels for this 38 * @run_mask: value mask for regulator voltages at 'run' state 39 * @run_on_mask: enable mask for regulator at 'run' state 41 * @idle_mask: value mask for regulator voltages at 'idle' state 42 * @idle_on_mask: enable mask for regulator at 'idle' state 44 * @suspend_mask: value mask for regulator voltages at 'suspend' state 45 * @suspend_on_mask: enable mask for regulator at 'suspend' state 47 * @lpsr_mask: value mask for regulator voltages at 'lpsr' state [all …]
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/Linux-v5.10/drivers/usb/serial/ |
D | io_16654.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and 22 // above are used internally to indicate that we must enable access 27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR. 32 #define IER 1 // ! Interrupt Enable Register 44 #define XON1 12 // Bank2[ 4 ] Xon-1 45 #define XON2 13 // Bank2[ 5 ] Xon-2 46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1 47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2 57 #define IER_RX 0x01 // Enable receive interrupt [all …]
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/Linux-v5.10/drivers/media/platform/davinci/ |
D | vpif.h | 4 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ 147 /* Macro for Generating mask */ 153 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos) 176 /* Mask various length */ 191 /* bit position of clock and channel enable in vpif_chn_ctrl register */ 270 /* inline function to enable/disable channel0 */ 271 static inline void enable_channel0(int enable) in enable_channel0() argument 273 if (enable) in enable_channel0() 279 /* inline function to enable/disable channel1 */ 280 static inline void enable_channel1(int enable) in enable_channel1() argument [all …]
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/Linux-v5.10/include/uapi/linux/ |
D | serial_reg.h | 1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ 24 #define UART_IER 1 /* Out: Interrupt Enable Register */ 25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ 36 #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ 49 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 76 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/regulator/ |
D | ti-abb-regulator.txt | 4 - compatible: Should be one of: 5 - "ti,abb-v1" for older SoCs like OMAP3 6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5 7 - "ti,abb-v3" for a generic definition where setup and control registers are 9 - reg: Address and length of the register set for the device. It contains 10 the information of registers in the same order as described by reg-names 11 - reg-names: Should contain the reg names 12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2) 13 - "control-address" - contains control register address of ABB module (ti,abb-v3) 14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3) [all …]
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/Linux-v5.10/drivers/soc/mediatek/ |
D | mtk-infracfg.c | 1 // SPDX-License-Identifier: GPL-2.0-only 21 * mtk_infracfg_set_bus_protection - enable bus protection 23 * @mask: The mask containing the protection bits to be enabled. 25 * by regmap_update_bits with enable register(PROTECTEN) or 32 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument 39 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection() 40 mask); in mtk_infracfg_set_bus_protection() 42 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection() 45 val, (val & mask) == mask, in mtk_infracfg_set_bus_protection() 52 * mtk_infracfg_clear_bus_protection - disable bus protection [all …]
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/Linux-v5.10/include/sound/ |
D | ak4113.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 20 /* interrupt0 mask */ 22 /* interrupt1 mask */ 24 /* DAT mask & DTS select */ 50 /* Q-subcode address + control */ 52 /* Q-subcode track */ 54 /* Q-subcode index */ 56 /* Q-subcode minute */ 58 /* Q-subcode second */ 60 /* Q-subcode frame */ [all …]
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D | ak4114.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */ 16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */ 33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */ 34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */ 35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */ 36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */ 37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */ 38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */ 39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */ [all …]
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/Linux-v5.10/drivers/iio/imu/st_lsm6dsx/ |
D | st_lsm6dsx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 26 #define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c" 28 #define ST_LSM9DS1_DEV_NAME "lsm9ds1-imu" 60 #define ST_LSM6DSX_SHIFT_VAL(val, mask) (((val) << __ffs(mask)) & (mask)) argument 103 u8 mask; member 136 * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings 139 * @fifo_th: FIFO threshold register info (addr + mask). 140 * @fifo_diff: FIFO diff status register info (addr + mask). 144 int (*update_fifo)(struct st_lsm6dsx_sensor *sensor, bool enable); 148 u16 mask; member [all …]
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/Linux-v5.10/arch/m68k/include/asm/ |
D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 /* include/asm-m68knommu/MC68328.h: '328 control registers 8 * Based on include/asm-m68knommu/MC68332.h 26 * 0xFFFFF0xx -- System Control 36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ 39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ 42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */ 45 * Mask Revision Register 52 * 0xFFFFF1xx -- Chip-Select logic 58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control [all …]
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/Linux-v5.10/drivers/input/misc/ |
D | pmic8xxx-pwrkey.c | 1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 29 /* Regulator master enable addresses */ 72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information 108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend() 118 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume() 130 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local 133 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown() 134 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown() 144 mask = PON_CNTL_1_PULL_UP_EN | PON_CNTL_1_USB_PWR_EN; in pmic8xxx_pwrkey_shutdown() [all …]
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/Linux-v5.10/drivers/net/ethernet/xilinx/ |
D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. 39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */ 52 /* Enable Length/Type error checking for incoming frames. When this option is 60 /* Enable the transmitter. Default: enabled (set) */ 63 /* Enable the receiver. Default: enabled (set) */ 103 #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */ 104 #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */ 147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ 150 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ [all …]
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/Linux-v5.10/drivers/mfd/ |
D | stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) ST-Ericsson SA 2010 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 27 * struct stmpe_platform_data - STMPE platform data 29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 31 * @autosleep: bool to enable/disable stmpe autosleep 49 return stmpe->variant->enable(stmpe, blocks, true); in __stmpe_enable() 54 return stmpe->variant->enable(stmpe, blocks, false); in __stmpe_disable() 61 ret = stmpe->ci->read_byte(stmpe, reg); in __stmpe_reg_read() 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); in __stmpe_reg_read() [all …]
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/Linux-v5.10/arch/sparc/include/asm/ |
D | lsu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 8 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/ 9 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/ 10 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/ 11 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/ 12 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/ 13 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/ 14 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */ 15 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */ 16 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */ [all …]
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