Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
51 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
52 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
57 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
58 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
63 #define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */
64 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
65 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
66 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
67 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
71 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
72 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
73 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
89 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
90 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
92 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
93 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94 #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
95 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
100 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
101 #define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */
103 #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
104 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
105 #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */
106 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
109 #define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */
110 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
111 #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */
117 #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
118 #define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */
120 #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */
121 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
122 #define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */
123 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
124 #define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
129 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
131 #define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */
134 #define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */
135 #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
136 #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */
137 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
142 #define SSCR1_ECRB BIT(26) /* Enable Clock request B */
143 #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */
145 #define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */
146 #define SSCR1_TTE BIT(30) /* TXD Tristate Enable */
147 #define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */
150 #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
186 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
187 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
190 #define SSIRF_RxThresh(x) ((x) - 1)
233 * pxa_ssp_write_reg - Write to a SSP register
241 __raw_writel(val, dev->mmio_base + reg); in pxa_ssp_write_reg()
245 * pxa_ssp_read_reg - Read from a SSP register
252 return __raw_readl(dev->mmio_base + reg); in pxa_ssp_read_reg()