Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
64 /* duty cycle, 0-100 */
67 /* hw-specific operation function pointers; most of these must be
73 /* enable rx */
86 /* enable tx FIFO space available interrupt */
137 /* low-speed carrier frequency limits (Hz) */
141 /* high-speed carrier frequency limits (Hz) */
153 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
158 * frequency A = (H - L) / (H + L). We can use this in order to honor the
159 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
194 * (EC - LPC I/O)
200 #define IT87_IER 0x01 /* interrupt enable register */
213 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
214 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
215 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
216 #define IT87_IEC 0x08 /* interrupt enable control */
217 #define IT87_BR 0x10 /* baud rate register enable */
221 #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */
223 #define IT87_RXEND 0x10 /* receiver demodulation enable */
224 #define IT87_RXEN 0x20 /* receiver enable */
225 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
229 #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */
232 #define IT87_TXRLE 0x08 /* transmitter run length enable */
233 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
235 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
236 * 0x30 -> 25 */
237 #define IT87_ILE 0x40 /* internal loopback enable */
241 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
243 #define IT87_CFQ 0xf8 /* carrier frequency mask */
247 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
250 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
251 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
255 #define IT87_II 0x06 /* interrupt identification mask */
282 #define IT85_C0IER 0x02 /* interrupt enable register */
301 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
303 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
304 * 0x0c -> 25 */
305 #define IT85_ILE 0x10 /* internal loopback enable */
309 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
310 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */
311 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
312 #define IT85_IEC 0x80 /* interrupt enable function control */
321 #define IT85_CFQ 0x1f /* carrier frequency mask */
325 #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */
327 #define IT85_RXEND 0x10 /* receiver demodulation enable */
329 #define IT85_RXEN 0x80 /* receiver enable */
332 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
334 #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */
337 #define IT85_TXRLE 0x40 /* transmitter run length enable */
342 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
343 #define IT85_DLLTE 0x08 /* DLL test enable */
348 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
351 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */
352 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
355 #define IT85_WCL 0x3f /* wakeup code length mask */
358 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
372 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
373 * selectable by a single bank-select bit that's mapped onto both banks. The
376 * reserved high-order bit are placed at the same offset in both banks in
384 #define IT8708_HRAE 0x80 /* high registers access enable */
389 #define IT8708_C0IER 0x02 /* interrupt enable register */
431 * a specific firmware running on the IT8512's embedded micro-controller.
432 * In addition of the embedded micro-controller, the IT8512 chip contains a
435 * micro-controller. The CIR module is only accessible by the
436 * micro-controller.
438 * The battery-backed SRAM module is accessible by the host CPU and the
439 * micro-controller. So one of the MC's firmware role is to act as a bridge
443 * communication protocol is not, so it was reverse-engineered.