Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
52 /* Enable Length/Type error checking for incoming frames. When this option is
60 /* Enable the transmitter. Default: enabled (set) */
63 /* Enable the receiver. Default: enabled (set) */
103 #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
104 #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
150 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
171 #define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
192 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
200 /* Transmit inter-frame gap adjustment value */
233 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
234 /* In-Band FCS enable (FCS not stripped) */
236 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
237 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
249 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
250 /* In-Band FCS enable (FCS not generated) */
252 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
253 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
254 /* Inter-frame gap adjustment enable */
258 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
259 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
263 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
264 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
265 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
266 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
267 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
268 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
269 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
270 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
271 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
274 #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
276 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
286 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
290 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
292 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
294 #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
296 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
297 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
298 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
299 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
311 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
312 #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
343 * struct axidma_bd - Axi Dma buffer descriptor layout
376 * struct axienet_local - axienet private per device data
387 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
465 * struct axiethernet_option - Used to set axi ethernet hardware options
468 * @m_or: Mask to be ORed for setting the option in the register
477 * axienet_ior - Memory mapped Axi Ethernet register read
487 return ioread32(lp->regs + offset); in axienet_ior()
496 * axienet_iow - Memory mapped Axi Ethernet register write
507 iowrite32(value, lp->regs + offset); in axienet_iow()