Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
22 // above are used internally to indicate that we must enable access
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
32 #define IER 1 // ! Interrupt Enable Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
57 #define IER_RX 0x01 // Enable receive interrupt
58 #define IER_TX 0x02 // Enable transmit interrupt
59 #define IER_RXS 0x04 // Enable receive status interrupt
60 #define IER_MDM 0x08 // Enable modem status interrupt
61 #define IER_SLEEP 0x10 // Enable sleep mode
62 #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt
63 #define IER_RTS 0x40 // Enable RTS interrupt
64 #define IER_CTS 0x80 // Enable CTS interrupt
65 #define IER_ENABLE_ALL 0xFF // Enable all ints
68 #define FCR_FIFO_EN 0x01 // Enable FIFOs
71 #define FCR_DMA_BLK 0x08 // Enable DMA block mode
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
77 #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level
93 #define ISR_INT_BITS_MASK 0x3E // Mask to isolate valid int causes
100 #define LCR_BITS_MASK 0x03 // Mask for bits/char field
104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
105 #define LCR_STOP_MASK 0x04 // Mask for stop bits field
112 #define LCR_PAR_MASK 0x38 // Mask for parity field
115 #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch
118 // and also the '654-only registers
125 #define MCR_MASTER_IE 0x08 // Enable interrupt outputs
127 #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode
128 #define MCR_IR_ENABLE 0x40 // Enable IrDA functions
144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
154 //-------------------------------
172 #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control
178 #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control
185 #define EFR_SWFC_MASK 0x0F // Mask for software flow control field
186 #define EFR_ENABLE_16654 0x10 // Enable 16C654 features
187 #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt