Searched +full:display +full:- +full:controller (Results 1 – 25 of 1008) sorted by relevance
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| /Linux-v6.1/Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 5 On this page, we try to keep track of acronyms related to the display
7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
53 Support for the CPU clock controller on msm8996 devices.
58 tristate "SDX55 and SDX65 APCS Clock Controller"
61 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
67 tristate "RPM based Clock Controller"
80 tristate "RPM over SMD based Clock Controller"
102 tristate "APQ8084 Global Clock Controller"
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| /Linux-v6.1/drivers/staging/fbtft/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 tristate "Support for small TFT LCD display modules"
14 tristate "FB driver for the AGM1264K-FL LCD display"
17 Framebuffer support for the AGM1264K-FL LCD display (two Samsung KS0108 compatible chips)
20 tristate "FB driver for the BD663474 LCD Controller"
26 tristate "FB driver for the HX8340BN LCD Controller"
32 tristate "FB driver for the HX8347D LCD Controller"
38 tristate "FB driver for the HX8353D LCD Controller"
44 tristate "FB driver for the HX8357D LCD Controller"
50 tristate "FB driver for the ILI9163 LCD Controller"
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| /Linux-v6.1/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra186-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
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| D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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| /Linux-v6.1/Documentation/devicetree/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
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| /Linux-v6.1/Documentation/devicetree/bindings/display/msm/ |
| D | dpu-msm8998.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for MSM8998 target
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
20 - const: qcom,msm8998-mdss
25 reg-names:
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| D | dpu-sc7180.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
20 - const: qcom,sc7180-mdss
25 reg-names:
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| D | dpu-sc7280.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7280
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
19 const: qcom,sc7280-mdss
24 reg-names:
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| D | dpu-qcm2290.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for QCM2290 target
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
20 - const: qcom,qcm2290-mdss
25 reg-names:
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| D | dpu-sdm845.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
20 - const: qcom,sdm845-mdss
25 reg-names:
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| D | dsi-controller-main.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: "../dsi-controller.yaml#"
18 - qcom,mdss-dsi-ctrl
19 - qcom,dsi-ctrl-6g-qcm2290
24 reg-names:
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| /Linux-v6.1/drivers/gpu/drm/sun4i/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Allwinner A10 Display Engine"
13 Display Engine. If M is selected the module will be called
14 sun4i-drm.
19 tristate "Allwinner A10/A10s/A20/A31 HDMI Controller Support"
24 SoC with an HDMI controller.
33 SoC with an HDMI controller and want to use CEC.
36 tristate "Support for Allwinner A10 Display Engine Backend"
41 original Allwinner Display Engine, which has a backend to
43 selected the module will be called sun4i-backend.
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| /Linux-v6.1/drivers/staging/olpc_dcon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 tristate "One Laptop Per Child Display CONtroller support"
10 secondary Display CONtroller, or DCON. This secondary controller
11 is present in the video pipeline between the primary display
12 controller (integrate into the processor or chipset) and the LCD
13 panel. It allows the main processor/display controller to be
14 completely powered off while still retaining an image on the display.
15 This controller is only available on OLPC platforms. Unless you have
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| /Linux-v6.1/Documentation/devicetree/bindings/display/ |
| D | xylon,logicvc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
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| D | intel,keembay-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Devicetree bindings for Intel Keem Bay display controller
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-display
19 - description: LCD registers range
21 reg-names:
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| /Linux-v6.1/Documentation/gpu/ |
| D | tegra.rst | 2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
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| /Linux-v6.1/Documentation/devicetree/bindings/display/panel/ |
| D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 display panels. It doesn't constitue a device tree binding specification by
24 width-mm:
29 height-mm:
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| /Linux-v6.1/drivers/video/fbdev/mmp/hw/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "mmp display controller hw support"
7 Marvell MMP display hw controller support
8 this controller is used on Marvell PXA910 and
12 bool "mmp display controller spi port"
16 Marvell MMP display hw controller spi port support
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| /Linux-v6.1/drivers/platform/surface/aggregator/ |
| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Provides access to a SAM-over-SSH connected EC via a controller device.
10 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
24 #include <linux/surface_aggregator/controller.h>
28 #include "controller.h"
34 /* -- Static controller reference. ------------------------------------------ */
37 * Main controller reference. The corresponding lock must be held while
44 * ssam_get_controller() - Get reference to SSAM controller.
46 * Returns a reference to the SSAM controller of the system or %NULL if there
49 * controller, thus the calling party must ensure that ssam_controller_put()
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| /Linux-v6.1/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos7-decon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 DECON (Display and Enhancement Controller) is the Display Controller for the
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| /Linux-v6.1/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 1 The Exynos display port interface should be configured based on
5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
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| /Linux-v6.1/drivers/gpu/drm/xlnx/ |
| D | zynqmp_disp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
28 #include <linux/dma-mapping.h>
43 * --------
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
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| /Linux-v6.1/drivers/gpu/drm/msm/dp/ |
| D | dp_parser.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
11 #include <linux/phy/phy-dp.h>
15 #define DP_LABEL "MDSS DP DISPLAY"
51 * struct dp_display_data - display related device tree data.
53 * @ctrl_node: referece to controller device
55 * @is_active: is the controller currently active
56 * @name: name of the display
57 * @display_type: type of the display
68 * struct dp_ctrl_resource - controller's IO related data
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| /Linux-v6.1/Documentation/devicetree/bindings/display/atmel/ |
| D | hlcdc-dc.txt | 1 Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
3 The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
4 See ../../mfd/atmel-hlcdc.txt for more details.
7 - compatible: value should be "atmel,hlcdc-display-controller"
8 - pinctrl-names: the pin control state names. Should contain "default".
9 - pinctrl-0: should contain the default pinctrl states.
10 - #address-cells: should be set to 1.
11 - #size-cells: should be set to 0.
20 according to ../../media/video-interfaces.txt, specifically
21 - bus-width: recognized values are <12>, <16>, <18> and <24>, and
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