Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7280
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
19 const: qcom,sc7280-mdss
24 reg-names:
27 power-domains:
32 - description: Display AHB clock from gcc
33 - description: Display AHB clock from dispcc
34 - description: Display core clock
36 clock-names:
38 - const: iface
39 - const: ahb
40 - const: core
45 interrupt-controller: true
47 "#address-cells": true
49 "#size-cells": true
51 "#interrupt-cells":
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
62 - description: Interconnect path specifying the port ids for data bus
64 interconnect-names:
65 const: mdp0-mem
69 - description: MDSS_CORE reset
72 "^display-controller@[0-9a-f]+$":
79 const: qcom,sc7280-dpu
83 - description: Address offset and size for mdp register set
84 - description: Address offset and size for vbif register set
86 reg-names:
88 - const: mdp
89 - const: vbif
93 - description: Display hf axi clock
94 - description: Display sf axi clock
95 - description: Display ahb clock
96 - description: Display lut clock
97 - description: Display core clock
98 - description: Display vsync clock
100 clock-names:
102 - const: bus
103 - const: nrt_bus
104 - const: iface
105 - const: lut
106 - const: core
107 - const: vsync
112 power-domains:
115 operating-points-v2: true
116 opp-table:
137 - port@0
140 - compatible
141 - reg
142 - reg-names
143 - clocks
144 - interrupts
145 - power-domains
146 - operating-points-v2
147 - ports
150 - compatible
151 - reg
152 - reg-names
153 - power-domains
154 - clocks
155 - interrupts
156 - interrupt-controller
157 - iommus
158 - ranges
163 - |
164 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
165 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
166 #include <dt-bindings/interrupt-controller/arm-gic.h>
167 #include <dt-bindings/interconnect/qcom,sc7280.h>
168 #include <dt-bindings/power/qcom-rpmpd.h>
170 display-subsystem@ae00000 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "qcom,sc7280-mdss";
175 reg-names = "mdss";
176 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
180 clock-names = "iface",
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 interconnect-names = "mdp0-mem";
194 display-controller@ae01000 {
195 compatible = "qcom,sc7280-dpu";
199 reg-names = "mdp", "vbif";
207 clock-names = "bus",
214 interrupt-parent = <&mdss>;
216 power-domains = <&rpmhpd SC7280_CX>;
217 operating-points-v2 = <&mdp_opp_table>;
220 #address-cells = <1>;
221 #size-cells = <0>;
226 remote-endpoint = <&dsi0_in>;
233 remote-endpoint = <&edp_in>;