Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for QCM2290 target
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
20 - const: qcom,qcm2290-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
34 - description: Display AXI clock
35 - description: Display core clock
37 clock-names:
39 - const: iface
40 - const: bus
41 - const: core
46 interrupt-controller: true
48 "#address-cells": true
50 "#size-cells": true
52 "#interrupt-cells":
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
64 - description: Interconnect path specifying the port ids for data bus
66 interconnect-names:
67 const: mdp0-mem
71 - description: MDSS_CORE reset
74 "^display-controller@[0-9a-f]+$":
82 - const: qcom,qcm2290-dpu
86 - description: Address offset and size for mdp register set
87 - description: Address offset and size for vbif register set
89 reg-names:
91 - const: mdp
92 - const: vbif
96 - description: Display AXI clock from gcc
97 - description: Display AHB clock from dispcc
98 - description: Display core clock from dispcc
99 - description: Display lut clock from dispcc
100 - description: Display vsync clock from dispcc
102 clock-names:
104 - const: bus
105 - const: iface
106 - const: core
107 - const: lut
108 - const: vsync
113 power-domains:
116 operating-points-v2: true
117 opp-table:
134 - port@0
137 - compatible
138 - reg
139 - reg-names
140 - clocks
141 - interrupts
142 - power-domains
143 - operating-points-v2
144 - ports
147 - compatible
148 - reg
149 - reg-names
150 - power-domains
151 - clocks
152 - interrupts
153 - interrupt-controller
154 - iommus
155 - ranges
160 - |
161 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
162 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
163 #include <dt-bindings/interrupt-controller/arm-gic.h>
164 #include <dt-bindings/interconnect/qcom,qcm2290.h>
165 #include <dt-bindings/power/qcom-rpmpd.h>
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "qcom,qcm2290-mdss";
172 reg-names = "mdss";
173 power-domains = <&dispcc MDSS_GDSC>;
177 clock-names = "iface", "bus", "core";
180 interrupt-controller;
181 #interrupt-cells = <1>;
184 interconnect-names = "mdp0-mem";
190 mdss_mdp: display-controller@5e01000 {
191 compatible = "qcom,qcm2290-dpu";
194 reg-names = "mdp", "vbif";
201 clock-names = "bus", "iface", "core", "lut", "vsync";
203 operating-points-v2 = <&mdp_opp_table>;
204 power-domains = <&rpmpd QCM2290_VDDCX>;
206 interrupt-parent = <&mdss>;
210 #address-cells = <1>;
211 #size-cells = <0>;
216 remote-endpoint = <&dsi0_in>;