Lines Matching +full:display +full:- +full:controller

2  drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18   - A host1x driver that provides infrastructure and access to the host1x
21   - A KMS driver that supports the display controllers as well as a number of
24   - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
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50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
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58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
64 The display hardware has remained mostly backwards compatible over the various
68 Display Controllers
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71 Tegra SoCs have two display controllers, each of which can be associated with
72 zero or more outputs. Outputs can also share a single display controller, but
73 only if they run with compatible display timings. Two display controllers can
75 on two outputs don't match. A display controller is modelled as a CRTC in KMS
78 On Tegra186, the number of display controllers has been increased to three. A
79 display controller can no longer drive all of the outputs. While two of these
86 A display controller controls a set of windows that can be used to composite
94 content. In KMS, each window is modelled as a plane. Each display controller
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102 very simple RGB interfaces (one per display controller), recent generations no
123 Although Tegra has supported DSI since Tegra30, the controller has changed in
131 eDP was first introduced in Tegra124 where it was used to drive the display
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146 with Tegra-specific flags. This is useful for buffers that should be tiled, or
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