Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: "../dsi-controller.yaml#"
18 - qcom,mdss-dsi-ctrl
19 - qcom,dsi-ctrl-6g-qcm2290
24 reg-names:
32 - description: Display byte clock
33 - description: Display byte interface clock
34 - description: Display pixel clock
35 - description: Display escape clock
36 - description: Display AHB clock
37 - description: Display AXI clock
39 clock-names:
41 - const: byte
42 - const: byte_intf
43 - const: pixel
44 - const: core
45 - const: iface
46 - const: bus
51 phy-names:
54 "#address-cells": true
56 "#size-cells": true
58 syscon-sfpb:
62 qcom,dual-dsi-mode:
65 Indicates if the DSI controller is driving a panel which needs
68 assigned-clocks:
73 assigned-clock-parents:
78 power-domains:
81 operating-points-v2: true
86 Contains DSI controller input and output ports as children, each
91 $ref: "/schemas/graph.yaml#/$defs/port-base"
94 Input endpoints of the controller.
97 $ref: /schemas/media/video-interfaces.yaml#
100 data-lanes:
107 $ref: "/schemas/graph.yaml#/$defs/port-base"
110 Output endpoints of the controller.
113 $ref: /schemas/media/video-interfaces.yaml#
116 data-lanes:
123 - port@0
124 - port@1
127 - compatible
128 - reg
129 - reg-names
130 - interrupts
131 - clocks
132 - clock-names
133 - phys
134 - phy-names
135 - assigned-clocks
136 - assigned-clock-parents
137 - power-domains
138 - operating-points-v2
139 - ports
144 - |
145 #include <dt-bindings/interrupt-controller/arm-gic.h>
146 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
147 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
148 #include <dt-bindings/power/qcom-rpmpd.h>
151 compatible = "qcom,mdss-dsi-ctrl";
153 reg-names = "dsi_ctrl";
155 #address-cells = <1>;
156 #size-cells = <0>;
158 interrupt-parent = <&mdss>;
167 clock-names = "byte",
175 phy-names = "dsi";
177 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
178 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
180 power-domains = <&rpmhpd SC7180_CX>;
181 operating-points-v2 = <&dsi_opp_table>;
184 #address-cells = <1>;
185 #size-cells = <0>;
190 remote-endpoint = <&dpu_intf1_out>;
197 remote-endpoint = <&sn65dsi86_in>;
198 data-lanes = <0 1 2 3>;