Searched +full:d +full:- +full:cache +full:- +full:sets (Results 1 – 25 of 550) sorted by relevance
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/Linux-v6.1/arch/arm64/boot/dts/amazon/ |
D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "amazon,al-alpine-v3"; 14 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <1>; 21 #size-cells = <0>; 25 compatible = "arm,cortex-a72"; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/amd/ |
D | amd-seattle-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 8 cpu-map { 45 compatible = "arm,cortex-a57"; 47 enable-method = "psci"; 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/marvell/ |
D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap807.dtsi" 12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/ti/ |
D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; [all …]
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D | k3-am625.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]
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D | k3-am62a7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62a.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]
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D | k3-am642.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 8 /dts-v1/; 10 #include "k3-am64.dtsi" 14 #address-cells = <1>; 15 #size-cells = <0>; 17 cpu-map { 30 compatible = "arm,cortex-a53"; 33 enable-method = "psci"; 34 i-cache-size = <0x8000>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/freescale/ |
D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; [all …]
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D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 // Device Tree Include file for Layerscape-LX2160A family SoC. 5 // Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
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D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2020 NXP 8 #include <dt-bindings/clock/imx8-clock.h> 9 #include <dt-bindings/clock/imx8-lpcg.h> 10 #include <dt-bindings/firmware/imx/rsrc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi" 3 #include "bcm2835-rpi-common.dtsi" 11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 14 compatible = "brcm,bcm2836-l1-intc"; 16 interrupt-controller; 17 #interrupt-cells = <2>; 18 interrupt-parent = <&local_intc>; 22 arm-pmu { 23 compatible = "arm,cortex-a53-pmu"; 24 interrupt-parent = <&local_intc>; [all …]
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D | bcm2836.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include "bcm2835-common.dtsi" 4 #include "bcm2835-rpi-common.dtsi" 12 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 15 compatible = "brcm,bcm2836-l1-intc"; 17 interrupt-controller; 18 #interrupt-cells = <2>; 19 interrupt-parent = <&local_intc>; 23 arm-pmu { 24 compatible = "arm,cortex-a7-pmu"; [all …]
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D | bcm2835.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include "bcm2835-common.dtsi" 4 #include "bcm2835-rpi-common.dtsi" 10 #address-cells = <1>; 11 #size-cells = <0>; 15 compatible = "arm,arm1176jzf-s"; 17 /* Source for d/i-cache-line-size and d/i-cache-sets 19 * /h/level-one-memory-system/cache-organization?lang=en 21 * Source for d/i-cache-size 24 * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU [all …]
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/Linux-v6.1/arch/arm64/boot/dts/arm/ |
D | juno-r2.dts | 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 28 stdout-path = "serial0:115200n8"; [all …]
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D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd. 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 27 stdout-path = "serial0:115200n8"; 31 compatible = "arm,psci-0.2"; [all …]
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D | juno-r1.dts | 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 28 stdout-path = "serial0:115200n8"; [all …]
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/Linux-v6.1/arch/riscv/boot/dts/sifive/ |
D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; [all …]
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D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c000", "sifive,fu740"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; [all …]
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/Linux-v6.1/arch/riscv/kernel/ |
D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only 22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group() 23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group() 32 * that cores have a homonogenous view of the cache hierarchy. That in get_cacheinfo() 33 * happens to be the case for the current set of RISC-V systems, but in get_cacheinfo() 42 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo() 43 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo() 44 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo() 55 return this_leaf ? this_leaf->size : 0; in get_cache_size() 62 return this_leaf ? (this_leaf->ways_of_associativity << 16 | in get_cache_geometry() [all …]
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/Linux-v6.1/arch/riscv/boot/dts/microchip/ |
D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/tesla/ |
D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2022 Tesla, Inc. 11 #include <dt-bindings/clock/fsd-clk.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 38 #address-cells = <2>; [all …]
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/Linux-v6.1/arch/riscv/boot/dts/starfive/ |
D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; 18 #size-cells = <0>; 21 compatible = "sifive,u74-mc", "riscv"; 23 d-cache-block-size = <64>; [all …]
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/Linux-v6.1/arch/mips/mm/ |
D | c-octeon.c | 6 * Copyright (C) 2005-2007 Cavium Networks 20 #include <asm/cpu-features.h> 21 #include <asm/cpu-type.h> 35 * tagged cache. No flushing is needed 49 * Flush local I-cache for the specified range. 58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores 82 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores() 104 * octeon_flush_cache_mm - flush all memory associated with a memory context. 128 * octeon_flush_cache_range - Flush a range out of a vma 137 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range() [all …]
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