Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
302 compatible = "cache";
303 cache-size = <0x100000>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
309 cluster1_l2: l2-cache1 {
310 compatible = "cache";
311 cache-size = <0x100000>;
312 cache-line-size = <64>;
313 cache-sets = <1024>;
314 cache-level = <2>;
317 cluster2_l2: l2-cache2 {
318 compatible = "cache";
319 cache-size = <0x100000>;
320 cache-line-size = <64>;
321 cache-sets = <1024>;
322 cache-level = <2>;
325 cluster3_l2: l2-cache3 {
326 compatible = "cache";
327 cache-size = <0x100000>;
328 cache-line-size = <64>;
329 cache-sets = <1024>;
330 cache-level = <2>;
333 cluster4_l2: l2-cache4 {
334 compatible = "cache";
335 cache-size = <0x100000>;
336 cache-line-size = <64>;
337 cache-sets = <1024>;
338 cache-level = <2>;
341 cluster5_l2: l2-cache5 {
342 compatible = "cache";
343 cache-size = <0x100000>;
344 cache-line-size = <64>;
345 cache-sets = <1024>;
346 cache-level = <2>;
349 cluster6_l2: l2-cache6 {
350 compatible = "cache";
351 cache-size = <0x100000>;
352 cache-line-size = <64>;
353 cache-sets = <1024>;
354 cache-level = <2>;
357 cluster7_l2: l2-cache7 {
358 compatible = "cache";
359 cache-size = <0x100000>;
360 cache-line-size = <64>;
361 cache-sets = <1024>;
362 cache-level = <2>;
365 cpu_pw15: cpu-pw15 {
366 compatible = "arm,idle-state";
367 idle-state-name = "PW15";
368 arm,psci-suspend-param = <0x0>;
369 entry-latency-us = <2000>;
370 exit-latency-us = <2000>;
371 min-residency-us = <6000>;
375 gic: interrupt-controller@6000000 {
376 compatible = "arm,gic-v3";
383 #interrupt-cells = <3>;
384 #address-cells = <2>;
385 #size-cells = <2>;
387 interrupt-controller;
390 its: gic-its@6020000 {
391 compatible = "arm,gic-v3-its";
392 msi-controller;
398 compatible = "arm,armv8-timer";
406 compatible = "arm,cortex-a72-pmu";
411 compatible = "arm,psci-0.2";
416 // DRAM space - 1, size : 2 GB DRAM
421 ddr1: memory-controller@1080000 {
422 compatible = "fsl,qoriq-memory-controller";
425 little-endian;
428 ddr2: memory-controller@1090000 {
429 compatible = "fsl,qoriq-memory-controller";
432 little-endian;
435 // One clock unit-sysclk node which bootloader require during DT fix-up
437 compatible = "fixed-clock";
438 #clock-cells = <0>;
439 clock-frequency = <100000000>; // fixed up by bootloader
440 clock-output-names = "sysclk";
443 thermal-zones {
444 cluster6-7 {
445 polling-delay-passive = <1000>;
446 polling-delay = <5000>;
447 thermal-sensors = <&tmu 0>;
450 cluster6_7_alert: cluster6-7-alert {
456 cluster6_7_crit: cluster6-7-crit {
463 cooling-maps {
466 cooling-device =
487 ddr-cluster5 {
488 polling-delay-passive = <1000>;
489 polling-delay = <5000>;
490 thermal-sensors = <&tmu 1>;
493 ddr-cluster5-alert {
499 ddr-cluster5-crit {
508 polling-delay-passive = <1000>;
509 polling-delay = <5000>;
510 thermal-sensors = <&tmu 2>;
513 wriop-alert {
519 wriop-crit {
527 dce-qbman-hsio2 {
528 polling-delay-passive = <1000>;
529 polling-delay = <5000>;
530 thermal-sensors = <&tmu 3>;
533 dce-qbman-alert {
539 dce-qbman-crit {
547 ccn-dpaa-tbu {
548 polling-delay-passive = <1000>;
549 polling-delay = <5000>;
550 thermal-sensors = <&tmu 4>;
553 ccn-dpaa-alert {
559 ccn-dpaa-crit {
567 cluster4-hsio3 {
568 polling-delay-passive = <1000>;
569 polling-delay = <5000>;
570 thermal-sensors = <&tmu 5>;
573 clust4-hsio3-alert {
579 clust4-hsio3-crit {
587 cluster2-3 {
588 polling-delay-passive = <1000>;
589 polling-delay = <5000>;
590 thermal-sensors = <&tmu 6>;
593 cluster2-3-alert {
599 cluster2-3-crit {
609 compatible = "simple-bus";
610 #address-cells = <2>;
611 #size-cells = <2>;
613 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
616 compatible = "fsl,lynx-28g";
618 #phy-cells = <1>;
622 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
623 fsl,sec-era = <10>;
624 #address-cells = <1>;
625 #size-cells = <1>;
629 dma-coherent;
633 compatible = "fsl,sec-v5.0-job-ring",
634 "fsl,sec-v4.0-job-ring";
640 compatible = "fsl,sec-v5.0-job-ring",
641 "fsl,sec-v4.0-job-ring";
647 compatible = "fsl,sec-v5.0-job-ring",
648 "fsl,sec-v4.0-job-ring";
654 compatible = "fsl,sec-v5.0-job-ring",
655 "fsl,sec-v4.0-job-ring";
661 clockgen: clock-controller@1300000 {
662 compatible = "fsl,lx2160a-clockgen";
664 #clock-cells = <2>;
669 compatible = "fsl,lx2160a-dcfg", "syscon";
671 little-endian;
675 compatible = "fsl,ls1028a-sfp";
679 clock-names = "sfp";
683 compatible = "fsl,lx2160a-isc", "syscon";
685 little-endian;
686 #address-cells = <1>;
687 #size-cells = <1>;
690 extirq: interrupt-controller@14 {
691 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
692 #interrupt-cells = <2>;
693 #address-cells = <0>;
694 interrupt-controller;
696 interrupt-map =
709 interrupt-map-mask = <0xf 0x0>;
714 compatible = "fsl,qoriq-tmu";
717 fsl,tmu-range = <0x800000e6 0x8001017d>;
718 fsl,tmu-calibration =
723 little-endian;
724 #thermal-sensor-cells = <1>;
728 compatible = "fsl,vf610-i2c";
729 #address-cells = <1>;
730 #size-cells = <0>;
733 clock-names = "i2c";
736 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
741 compatible = "fsl,vf610-i2c";
742 #address-cells = <1>;
743 #size-cells = <0>;
746 clock-names = "i2c";
753 compatible = "fsl,vf610-i2c";
754 #address-cells = <1>;
755 #size-cells = <0>;
758 clock-names = "i2c";
765 compatible = "fsl,vf610-i2c";
766 #address-cells = <1>;
767 #size-cells = <0>;
770 clock-names = "i2c";
777 compatible = "fsl,vf610-i2c";
778 #address-cells = <1>;
779 #size-cells = <0>;
782 clock-names = "i2c";
785 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
790 compatible = "fsl,vf610-i2c";
791 #address-cells = <1>;
792 #size-cells = <0>;
795 clock-names = "i2c";
802 compatible = "fsl,vf610-i2c";
803 #address-cells = <1>;
804 #size-cells = <0>;
807 clock-names = "i2c";
814 compatible = "fsl,vf610-i2c";
815 #address-cells = <1>;
816 #size-cells = <0>;
819 clock-names = "i2c";
826 compatible = "nxp,lx2160a-fspi";
827 #address-cells = <1>;
828 #size-cells = <0>;
831 reg-names = "fspi_base", "fspi_mmap";
837 clock-names = "fspi_en", "fspi";
842 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
843 #address-cells = <1>;
844 #size-cells = <0>;
849 clock-names = "dspi";
850 spi-num-chipselects = <5>;
851 bus-num = <0>;
856 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
857 #address-cells = <1>;
858 #size-cells = <0>;
863 clock-names = "dspi";
864 spi-num-chipselects = <5>;
865 bus-num = <1>;
870 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
871 #address-cells = <1>;
872 #size-cells = <0>;
877 clock-names = "dspi";
878 spi-num-chipselects = <5>;
879 bus-num = <2>;
889 dma-coherent;
890 voltage-ranges = <1800 1800 3300 3300>;
891 sdhci,auto-cmd12;
892 little-endian;
893 bus-width = <4>;
903 dma-coherent;
904 voltage-ranges = <1800 1800 3300 3300>;
905 sdhci,auto-cmd12;
906 broken-cd;
907 little-endian;
908 bus-width = <4>;
913 compatible = "fsl,lx2160ar1-flexcan";
919 clock-names = "ipg", "per";
920 fsl,clk-source = /bits/ 8 <0>;
925 compatible = "fsl,lx2160ar1-flexcan";
931 clock-names = "ipg", "per";
932 fsl,clk-source = /bits/ 8 <0>;
937 compatible = "arm,sbsa-uart","arm,pl011";
940 current-speed = <115200>;
945 compatible = "arm,sbsa-uart","arm,pl011";
948 current-speed = <115200>;
953 compatible = "arm,sbsa-uart","arm,pl011";
956 current-speed = <115200>;
961 compatible = "arm,sbsa-uart","arm,pl011";
964 current-speed = <115200>;
969 compatible = "fsl,qoriq-gpio";
972 gpio-controller;
973 little-endian;
974 #gpio-cells = <2>;
975 interrupt-controller;
976 #interrupt-cells = <2>;
980 compatible = "fsl,qoriq-gpio";
983 gpio-controller;
984 little-endian;
985 #gpio-cells = <2>;
986 interrupt-controller;
987 #interrupt-cells = <2>;
991 compatible = "fsl,qoriq-gpio";
994 gpio-controller;
995 little-endian;
996 #gpio-cells = <2>;
997 interrupt-controller;
998 #interrupt-cells = <2>;
1002 compatible = "fsl,qoriq-gpio";
1005 gpio-controller;
1006 little-endian;
1007 #gpio-cells = <2>;
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1013 compatible = "arm,sbsa-gwdt";
1017 timeout-sec = <30>;
1020 rcpm: power-controller@1e34040 {
1021 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1023 #fsl,rcpm-wakeup-cells = <7>;
1024 little-endian;
1028 compatible = "fsl,lx2160a-ftm-alarm";
1030 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1039 snps,quirk-frame-length-adjustment = <0x20>;
1040 usb3-lpm-capable;
1042 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1051 snps,quirk-frame-length-adjustment = <0x20>;
1052 usb3-lpm-capable;
1054 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1059 compatible = "fsl,lx2160a-ahci";
1062 reg-names = "ahci", "sata-ecc";
1066 dma-coherent;
1071 compatible = "fsl,lx2160a-ahci";
1074 reg-names = "ahci", "sata-ecc";
1078 dma-coherent;
1083 compatible = "fsl,lx2160a-ahci";
1086 reg-names = "ahci", "sata-ecc";
1090 dma-coherent;
1095 compatible = "fsl,lx2160a-ahci";
1098 reg-names = "ahci", "sata-ecc";
1102 dma-coherent;
1107 compatible = "fsl,lx2160a-pcie";
1110 reg-names = "csr_axi_slave", "config_axi_slave";
1114 interrupt-names = "aer", "pme", "intr";
1115 #address-cells = <3>;
1116 #size-cells = <2>;
1118 dma-coherent;
1119 apio-wins = <8>;
1120 ppio-wins = <8>;
1121 bus-range = <0x0 0xff>;
1122 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1123 msi-parent = <&its>;
1124 #interrupt-cells = <1>;
1125 interrupt-map-mask = <0 0 0 7>;
1126 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1130 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1135 compatible = "fsl,lx2160a-pcie";
1138 reg-names = "csr_axi_slave", "config_axi_slave";
1142 interrupt-names = "aer", "pme", "intr";
1143 #address-cells = <3>;
1144 #size-cells = <2>;
1146 dma-coherent;
1147 apio-wins = <8>;
1148 ppio-wins = <8>;
1149 bus-range = <0x0 0xff>;
1150 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1151 msi-parent = <&its>;
1152 #interrupt-cells = <1>;
1153 interrupt-map-mask = <0 0 0 7>;
1154 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1158 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1163 compatible = "fsl,lx2160a-pcie";
1166 reg-names = "csr_axi_slave", "config_axi_slave";
1170 interrupt-names = "aer", "pme", "intr";
1171 #address-cells = <3>;
1172 #size-cells = <2>;
1174 dma-coherent;
1175 apio-wins = <256>;
1176 ppio-wins = <24>;
1177 bus-range = <0x0 0xff>;
1178 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1179 msi-parent = <&its>;
1180 #interrupt-cells = <1>;
1181 interrupt-map-mask = <0 0 0 7>;
1182 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1186 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1191 compatible = "fsl,lx2160a-pcie";
1194 reg-names = "csr_axi_slave", "config_axi_slave";
1198 interrupt-names = "aer", "pme", "intr";
1199 #address-cells = <3>;
1200 #size-cells = <2>;
1202 dma-coherent;
1203 apio-wins = <8>;
1204 ppio-wins = <8>;
1205 bus-range = <0x0 0xff>;
1206 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1207 msi-parent = <&its>;
1208 #interrupt-cells = <1>;
1209 interrupt-map-mask = <0 0 0 7>;
1210 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1214 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1219 compatible = "fsl,lx2160a-pcie";
1222 reg-names = "csr_axi_slave", "config_axi_slave";
1226 interrupt-names = "aer", "pme", "intr";
1227 #address-cells = <3>;
1228 #size-cells = <2>;
1230 dma-coherent;
1231 apio-wins = <256>;
1232 ppio-wins = <24>;
1233 bus-range = <0x0 0xff>;
1234 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1235 msi-parent = <&its>;
1236 #interrupt-cells = <1>;
1237 interrupt-map-mask = <0 0 0 7>;
1238 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1242 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1247 compatible = "fsl,lx2160a-pcie";
1250 reg-names = "csr_axi_slave", "config_axi_slave";
1254 interrupt-names = "aer", "pme", "intr";
1255 #address-cells = <3>;
1256 #size-cells = <2>;
1258 dma-coherent;
1259 apio-wins = <8>;
1260 ppio-wins = <8>;
1261 bus-range = <0x0 0xff>;
1262 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1263 msi-parent = <&its>;
1264 #interrupt-cells = <1>;
1265 interrupt-map-mask = <0 0 0 7>;
1266 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1270 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1275 compatible = "arm,mmu-500";
1277 #iommu-cells = <1>;
1278 #global-interrupts = <14>;
1283 // global non-secure fault
1285 // combined non-secure
1287 // performance counter interrupts 0-9
1363 dma-coherent;
1367 compatible = "fsl,dpaa2-console";
1371 ptp-timer@8b95000 {
1372 compatible = "fsl,dpaa2-ptp";
1376 little-endian;
1377 fsl,extts-fifo;
1380 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1382 compatible = "fsl,fman-memac-mdio";
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 little-endian;
1388 clock-frequency = <2500000>;
1395 compatible = "fsl,fman-memac-mdio";
1398 little-endian;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 clock-frequency = <2500000>;
1408 compatible = "fsl,fman-memac-mdio";
1410 little-endian;
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1415 pcs1: ethernet-phy@0 {
1421 compatible = "fsl,fman-memac-mdio";
1423 little-endian;
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1428 pcs2: ethernet-phy@0 {
1434 compatible = "fsl,fman-memac-mdio";
1436 little-endian;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1441 pcs3: ethernet-phy@0 {
1447 compatible = "fsl,fman-memac-mdio";
1449 little-endian;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1454 pcs4: ethernet-phy@0 {
1460 compatible = "fsl,fman-memac-mdio";
1462 little-endian;
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1467 pcs5: ethernet-phy@0 {
1473 compatible = "fsl,fman-memac-mdio";
1475 little-endian;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1480 pcs6: ethernet-phy@0 {
1486 compatible = "fsl,fman-memac-mdio";
1488 little-endian;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1493 pcs7: ethernet-phy@0 {
1499 compatible = "fsl,fman-memac-mdio";
1501 little-endian;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1506 pcs8: ethernet-phy@0 {
1512 compatible = "fsl,fman-memac-mdio";
1514 little-endian;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1519 pcs9: ethernet-phy@0 {
1525 compatible = "fsl,fman-memac-mdio";
1527 little-endian;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1532 pcs10: ethernet-phy@0 {
1538 compatible = "fsl,fman-memac-mdio";
1540 little-endian;
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1545 pcs11: ethernet-phy@0 {
1551 compatible = "fsl,fman-memac-mdio";
1553 little-endian;
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1558 pcs12: ethernet-phy@0 {
1564 compatible = "fsl,fman-memac-mdio";
1566 little-endian;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1571 pcs13: ethernet-phy@0 {
1577 compatible = "fsl,fman-memac-mdio";
1579 little-endian;
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1584 pcs14: ethernet-phy@0 {
1590 compatible = "fsl,fman-memac-mdio";
1592 little-endian;
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1597 pcs15: ethernet-phy@0 {
1603 compatible = "fsl,fman-memac-mdio";
1605 little-endian;
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1610 pcs16: ethernet-phy@0 {
1616 compatible = "fsl,fman-memac-mdio";
1618 little-endian;
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1623 pcs17: ethernet-phy@0 {
1629 compatible = "fsl,fman-memac-mdio";
1631 little-endian;
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1636 pcs18: ethernet-phy@0 {
1641 fsl_mc: fsl-mc@80c000000 {
1642 compatible = "fsl,qoriq-mc";
1645 msi-parent = <&its>;
1646 /* iommu-map property is fixed up by u-boot */
1647 iommu-map = <0 &smmu 0 0>;
1648 dma-coherent;
1649 #address-cells = <3>;
1650 #size-cells = <1>;
1653 * Region type 0x0 - MC portals
1654 * Region type 0x1 - QBMAN portals
1663 #address-cells = <1>;
1664 #size-cells = <0>;
1667 compatible = "fsl,qoriq-mc-dpmac";
1669 pcs-handle = <&pcs1>;
1673 compatible = "fsl,qoriq-mc-dpmac";
1675 pcs-handle = <&pcs2>;
1679 compatible = "fsl,qoriq-mc-dpmac";
1681 pcs-handle = <&pcs3>;
1685 compatible = "fsl,qoriq-mc-dpmac";
1687 pcs-handle = <&pcs4>;
1691 compatible = "fsl,qoriq-mc-dpmac";
1693 pcs-handle = <&pcs5>;
1697 compatible = "fsl,qoriq-mc-dpmac";
1699 pcs-handle = <&pcs6>;
1703 compatible = "fsl,qoriq-mc-dpmac";
1705 pcs-handle = <&pcs7>;
1709 compatible = "fsl,qoriq-mc-dpmac";
1711 pcs-handle = <&pcs8>;
1715 compatible = "fsl,qoriq-mc-dpmac";
1717 pcs-handle = <&pcs9>;
1721 compatible = "fsl,qoriq-mc-dpmac";
1723 pcs-handle = <&pcs10>;
1727 compatible = "fsl,qoriq-mc-dpmac";
1729 pcs-handle = <&pcs11>;
1733 compatible = "fsl,qoriq-mc-dpmac";
1735 pcs-handle = <&pcs12>;
1738 dpmac13: ethernet@d {
1739 compatible = "fsl,qoriq-mc-dpmac";
1741 pcs-handle = <&pcs13>;
1745 compatible = "fsl,qoriq-mc-dpmac";
1747 pcs-handle = <&pcs14>;
1751 compatible = "fsl,qoriq-mc-dpmac";
1753 pcs-handle = <&pcs15>;
1757 compatible = "fsl,qoriq-mc-dpmac";
1759 pcs-handle = <&pcs16>;
1763 compatible = "fsl,qoriq-mc-dpmac";
1765 pcs-handle = <&pcs17>;
1769 compatible = "fsl,qoriq-mc-dpmac";
1771 pcs-handle = <&pcs18>;
1779 compatible = "linaro,optee-tz";