Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
41 cpu-map {
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 clock-frequency = <2400000000>;
95 cpu-idle-states = <&CPU_SLEEP>;
96 i-cache-size = <0xc000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000>;
100 d-cache-line-size = <64>;
101 d-cache-sets = <256>;
102 next-level-cache = <&cpucl_l2>;
107 compatible = "arm,cortex-a72";
109 enable-method = "psci";
110 clock-frequency = <2400000000>;
111 cpu-idle-states = <&CPU_SLEEP>;
112 i-cache-size = <0xc000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <256>;
118 next-level-cache = <&cpucl_l2>;
123 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 clock-frequency = <2400000000>;
127 cpu-idle-states = <&CPU_SLEEP>;
128 i-cache-size = <0xc000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>;
134 next-level-cache = <&cpucl_l2>;
139 compatible = "arm,cortex-a72";
141 enable-method = "psci";
142 cpu-idle-states = <&CPU_SLEEP>;
143 i-cache-size = <0xc000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 d-cache-size = <0x8000>;
147 d-cache-line-size = <64>;
148 d-cache-sets = <256>;
149 next-level-cache = <&cpucl_l2>;
155 compatible = "arm,cortex-a72";
157 enable-method = "psci";
158 clock-frequency = <2400000000>;
159 cpu-idle-states = <&CPU_SLEEP>;
160 i-cache-size = <0xc000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <256>;
166 next-level-cache = <&cpucl_l2>;
171 compatible = "arm,cortex-a72";
173 enable-method = "psci";
174 clock-frequency = <2400000000>;
175 cpu-idle-states = <&CPU_SLEEP>;
176 i-cache-size = <0xc000>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <0x8000>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&cpucl_l2>;
187 compatible = "arm,cortex-a72";
189 enable-method = "psci";
190 clock-frequency = <2400000000>;
191 cpu-idle-states = <&CPU_SLEEP>;
192 i-cache-size = <0xc000>;
193 i-cache-line-size = <64>;
194 i-cache-sets = <256>;
195 d-cache-size = <0x8000>;
196 d-cache-line-size = <64>;
197 d-cache-sets = <256>;
198 next-level-cache = <&cpucl_l2>;
203 compatible = "arm,cortex-a72";
205 enable-method = "psci";
206 clock-frequency = <2400000000>;
207 cpu-idle-states = <&CPU_SLEEP>;
208 i-cache-size = <0xc000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <256>;
211 d-cache-size = <0x8000>;
212 d-cache-line-size = <64>;
213 d-cache-sets = <256>;
214 next-level-cache = <&cpucl_l2>;
220 compatible = "arm,cortex-a72";
222 enable-method = "psci";
223 clock-frequency = <2400000000>;
224 cpu-idle-states = <&CPU_SLEEP>;
225 i-cache-size = <0xc000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <256>;
228 d-cache-size = <0x8000>;
229 d-cache-line-size = <64>;
230 d-cache-sets = <256>;
231 next-level-cache = <&cpucl_l2>;
236 compatible = "arm,cortex-a72";
238 enable-method = "psci";
239 clock-frequency = <2400000000>;
240 cpu-idle-states = <&CPU_SLEEP>;
241 i-cache-size = <0xc000>;
242 i-cache-line-size = <64>;
243 i-cache-sets = <256>;
244 d-cache-size = <0x8000>;
245 d-cache-line-size = <64>;
246 d-cache-sets = <256>;
247 next-level-cache = <&cpucl_l2>;
252 compatible = "arm,cortex-a72";
254 enable-method = "psci";
255 clock-frequency = <2400000000>;
256 cpu-idle-states = <&CPU_SLEEP>;
257 i-cache-size = <0xc000>;
258 i-cache-line-size = <64>;
259 i-cache-sets = <256>;
260 d-cache-size = <0x8000>;
261 d-cache-line-size = <64>;
262 d-cache-sets = <256>;
263 next-level-cache = <&cpucl_l2>;
268 compatible = "arm,cortex-a72";
270 enable-method = "psci";
271 clock-frequency = <2400000000>;
272 cpu-idle-states = <&CPU_SLEEP>;
273 i-cache-size = <0xc000>;
274 i-cache-line-size = <64>;
275 i-cache-sets = <256>;
276 d-cache-size = <0x8000>;
277 d-cache-line-size = <64>;
278 d-cache-sets = <256>;
279 next-level-cache = <&cpucl_l2>;
282 cpucl_l2: l2-cache0 {
283 compatible = "cache";
284 cache-size = <0x400000>;
285 cache-line-size = <64>;
286 cache-sets = <4096>;
289 idle-states {
290 entry-method = "psci";
292 CPU_SLEEP: cpu-sleep {
293 idle-state-name = "c2";
294 compatible = "arm,idle-state";
295 local-timer-stop;
296 arm,psci-suspend-param = <0x0010000>;
297 entry-latency-us = <30>;
298 exit-latency-us = <75>;
299 min-residency-us = <300>;
304 arm-pmu {
305 compatible = "arm,armv8-pmuv3";
318 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
325 compatible = "arm,psci-1.0";
330 compatible = "arm,armv8-timer";
338 compatible = "fixed-clock";
339 clock-output-names = "fin_pll";
340 #clock-cells = <0>;
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <2>;
348 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
350 gic: interrupt-controller@10400000 {
351 compatible = "arm,gic-v3";
352 #interrupt-cells = <3>;
353 interrupt-controller;
360 compatible = "arm,mmu-500";
362 #iommu-cells = <2>;
363 #global-interrupts = <7>;
365 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
367 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
372 /* Per context non-secure context interrupts, 0-3 interrupts */
380 compatible = "arm,mmu-500";
382 #iommu-cells = <2>;
383 #global-interrupts = <11>;
385 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
396 /* Per context non-secure context interrupts, 0-7 interrupts */
408 compatible = "arm,mmu-500";
410 #iommu-cells = <2>;
411 #global-interrupts = <5>;
413 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
415 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
418 /* Per context non-secure context interrupts, 0-1 interrupts */
424 compatible = "arm,mmu-500";
426 #iommu-cells = <2>;
427 #global-interrupts = <5>;
429 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
431 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
434 /* Per context non-secure context interrupts, 0-1 interrupts */
439 clock_imem: clock-controller@10010000 {
440 compatible = "tesla,fsd-clock-imem";
442 #clock-cells = <1>;
447 clock-names = "fin_pll",
453 clock_cmu: clock-controller@11c10000 {
454 compatible = "tesla,fsd-clock-cmu";
456 #clock-cells = <1>;
458 clock-names = "fin_pll";
461 clock_csi: clock-controller@12610000 {
462 compatible = "tesla,fsd-clock-cam_csi";
464 #clock-cells = <1>;
466 clock-names = "fin_pll";
469 clock_mfc: clock-controller@12810000 {
470 compatible = "tesla,fsd-clock-mfc";
472 #clock-cells = <1>;
474 clock-names = "fin_pll";
477 clock_peric: clock-controller@14010000 {
478 compatible = "tesla,fsd-clock-peric";
480 #clock-cells = <1>;
487 clock-names = "fin_pll",
495 clock_fsys0: clock-controller@15010000 {
496 compatible = "tesla,fsd-clock-fsys0";
498 #clock-cells = <1>;
503 clock-names = "fin_pll",
509 clock_fsys1: clock-controller@16810000 {
510 compatible = "tesla,fsd-clock-fsys1";
512 #clock-cells = <1>;
516 clock-names = "fin_pll",
521 mdma0: dma-controller@10100000 {
525 #dma-cells = <1>;
527 clock-names = "apb_pclk";
531 mdma1: dma-controller@10110000 {
535 #dma-cells = <1>;
537 clock-names = "apb_pclk";
541 pdma0: dma-controller@14280000 {
545 #dma-cells = <1>;
547 clock-names = "apb_pclk";
551 pdma1: dma-controller@14290000 {
555 #dma-cells = <1>;
557 clock-names = "apb_pclk";
562 compatible = "samsung,exynos4210-uart";
566 dma-names = "rx", "tx";
569 clock-names = "uart", "clk_uart_baud0";
574 compatible = "samsung,exynos4210-uart";
578 dma-names = "rx", "tx";
581 clock-names = "uart", "clk_uart_baud0";
585 pmu_system_controller: system-controller@11400000 {
586 compatible = "samsung,exynos7-pmu", "syscon";
591 compatible = "samsung,exynos7-wdt";
594 samsung,syscon-phandle = <&pmu_system_controller>;
596 clock-names = "watchdog";
600 compatible = "samsung,exynos7-wdt";
603 samsung,syscon-phandle = <&pmu_system_controller>;
605 clock-names = "watchdog";
609 compatible = "samsung,exynos7-wdt";
612 samsung,syscon-phandle = <&pmu_system_controller>;
614 clock-names = "watchdog";
618 compatible = "samsung,exynos4210-pwm";
620 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
621 #pwm-cells = <3>;
623 clock-names = "timers";
628 compatible = "samsung,exynos4210-pwm";
630 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
631 #pwm-cells = <3>;
633 clock-names = "timers";
638 compatible = "samsung,exynos7-hsi2c";
641 #address-cells = <1>;
642 #size-cells = <0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&hs_i2c0_bus>;
646 clock-names = "hsi2c";
651 compatible = "samsung,exynos7-hsi2c";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&hs_i2c1_bus>;
659 clock-names = "hsi2c";
664 compatible = "samsung,exynos7-hsi2c";
667 #address-cells = <1>;
668 #size-cells = <0>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&hs_i2c2_bus>;
672 clock-names = "hsi2c";
677 compatible = "samsung,exynos7-hsi2c";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&hs_i2c3_bus>;
685 clock-names = "hsi2c";
690 compatible = "samsung,exynos7-hsi2c";
693 #address-cells = <1>;
694 #size-cells = <0>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&hs_i2c4_bus>;
698 clock-names = "hsi2c";
703 compatible = "samsung,exynos7-hsi2c";
706 #address-cells = <1>;
707 #size-cells = <0>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&hs_i2c5_bus>;
711 clock-names = "hsi2c";
716 compatible = "samsung,exynos7-hsi2c";
719 #address-cells = <1>;
720 #size-cells = <0>;
721 pinctrl-names = "default";
722 pinctrl-0 = <&hs_i2c6_bus>;
724 clock-names = "hsi2c";
729 compatible = "samsung,exynos7-hsi2c";
732 #address-cells = <1>;
733 #size-cells = <0>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&hs_i2c7_bus>;
737 clock-names = "hsi2c";
742 compatible = "tesla,fsd-pinctrl";
747 compatible = "tesla,fsd-pinctrl";
753 compatible = "tesla,fsd-pinctrl";
759 compatible = "tesla,fsd-spi";
763 dma-names = "tx", "rx";
764 #address-cells = <1>;
765 #size-cells = <0>;
768 clock-names = "spi", "spi_busclk0";
769 samsung,spi-src-clk = <0>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&spi0_bus>;
772 num-cs = <1>;
777 compatible = "tesla,fsd-spi";
781 dma-names = "tx", "rx";
782 #address-cells = <1>;
783 #size-cells = <0>;
786 clock-names = "spi", "spi_busclk0";
787 samsung,spi-src-clk = <0>;
788 pinctrl-names = "default";
789 pinctrl-0 = <&spi1_bus>;
790 num-cs = <1>;
795 compatible = "tesla,fsd-spi";
799 dma-names = "tx", "rx";
800 #address-cells = <1>;
801 #size-cells = <0>;
804 clock-names = "spi", "spi_busclk0";
805 samsung,spi-src-clk = <0>;
806 pinctrl-names = "default";
807 pinctrl-0 = <&spi2_bus>;
808 num-cs = <1>;
813 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
832 clock-names = "fin_pll", "mct";
836 compatible = "tesla,fsd-ufs";
841 reg-names = "hci", "vs_hci", "unipro", "ufsp";
845 clock-names = "core_clk", "sclk_unipro_main";
846 freq-table-hz = <0 0>, <0 0>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
850 phy-names = "ufs-phy";
854 ufs_phy: ufs-phy@15124000 {
855 compatible = "tesla,fsd-ufs-phy";
857 reg-names = "phy-pma";
858 samsung,pmu-syscon = <&pmu_system_controller>;
859 #phy-cells = <0>;
861 clock-names = "ref_clk";
866 #include "fsd-pinctrl.dtsi"