Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
45 i-cache-line-size = <64>;
46 i-cache-sets = <256>;
47 d-cache-size = <0x8000>;
48 d-cache-line-size = <64>;
49 d-cache-sets = <128>;
50 next-level-cache = <&L2_0>;
54 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 i-cache-size = <0x8000>;
59 i-cache-line-size = <64>;
60 i-cache-sets = <256>;
61 d-cache-size = <0x8000>;
62 d-cache-line-size = <64>;
63 d-cache-sets = <128>;
64 next-level-cache = <&L2_0>;
68 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 i-cache-size = <0x8000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <256>;
75 d-cache-size = <0x8000>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&L2_0>;
82 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 i-cache-size = <0x8000>;
87 i-cache-line-size = <64>;
88 i-cache-sets = <256>;
89 d-cache-size = <0x8000>;
90 d-cache-line-size = <64>;
91 d-cache-sets = <128>;
92 next-level-cache = <&L2_0>;
96 L2_0: l2-cache0 {
97 compatible = "cache";
98 cache-level = <2>;
99 cache-size = <0x40000>;
100 cache-line-size = <64>;
101 cache-sets = <512>;