Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
4 #include "bcm2835-rpi-common.dtsi"
12 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 compatible = "brcm,bcm2836-l1-intc";
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&local_intc>;
23 arm-pmu {
24 compatible = "arm,cortex-a7-pmu";
25 interrupt-parent = <&local_intc>;
30 compatible = "arm,armv7-timer";
31 interrupt-parent = <&local_intc>;
36 always-on;
40 #address-cells = <1>;
41 #size-cells = <0>;
42 enable-method = "brcm,bcm2836-smp";
44 /* Source for d/i-cache-line-size and d/i-cache-sets
45 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
46 * /About-the-L1-memory-system?lang=en
48 * Source for d/i-cache-size
54 compatible = "arm,cortex-a7";
56 clock-frequency = <800000000>;
57 d-cache-size = <0x8000>;
58 d-cache-line-size = <64>;
59 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-size = <0x8000>;
61 i-cache-line-size = <32>;
62 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
63 next-level-cache = <&l2>;
68 compatible = "arm,cortex-a7";
70 clock-frequency = <800000000>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <32>;
76 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
77 next-level-cache = <&l2>;
82 compatible = "arm,cortex-a7";
84 clock-frequency = <800000000>;
85 d-cache-size = <0x8000>;
86 d-cache-line-size = <64>;
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <32>;
90 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
91 next-level-cache = <&l2>;
96 compatible = "arm,cortex-a7";
98 clock-frequency = <800000000>;
99 d-cache-size = <0x8000>;
100 d-cache-line-size = <64>;
101 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
102 i-cache-size = <0x8000>;
103 i-cache-line-size = <32>;
104 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
105 next-level-cache = <&l2>;
108 /* Source for cache-line-size + cache-sets
109 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
110 * /About-the-L2-Memory-system?lang=en
111 * Source for cache-size
114 l2: l2-cache0 {
115 compatible = "cache";
116 cache-size = <0x80000>;
117 cache-line-size = <64>;
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
119 cache-level = <2>;
124 /* Make the BCM2835-style global interrupt controller be a child of the
125 * CPU-local interrupt controller.
128 compatible = "brcm,bcm2836-armctrl-ic";
130 interrupt-parent = <&local_intc>;
135 coefficients = <(-538) 407000>;
140 compatible = "brcm,bcm2836-thermal";