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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG0>;
293 resets = <&cru SRST_USB3OTG0>;
302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303 <&cru ACLK_USB3OTG1>;
[all …]
Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
141 clocks = <&cru ARMCLKB>;
185 clocks = <&cru SCLK_DDRC>;
232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
[all …]
Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 resets = <&cru SRST_MMC0>;
197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 resets = <&cru SRST_SDIO0>;
211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 resets = <&cru SRST_EMMC>;
[all …]
Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
47 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
71 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
249 clocks = <&cru HCLK_HOST>,
250 <&cru HCLK_OTG>,
251 <&cru SCLK_OTG_ADP>;
257 clocks = <&cru HCLK_SDMMC>,
258 <&cru SCLK_SDMMC>;
[all …]
Drk3568.dtsi14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
15 <&cru CLK_SATA0_RXOOB>;
55 <&cru PCLK_PCIE30PHY>;
57 resets = <&cru SRST_PCIE30PHY>;
68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
70 <&cru CLK_PCIE30X1_AUX_NDFT>;
101 resets = <&cru SRST_PCIE30X1_POWERUP>;
120 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
121 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
[all …]
Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
46 clocks = <&cru ARMCLK>;
189 assigned-clocks = <&cru USB480M>;
191 clocks = <&cru SCLK_USBPHY_REF>;
233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
272 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
285 clocks = <&cru PCLK_WDT>;
294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
32 resets = <&cru SRST_CORE0>;
36 clocks = <&cru ARMCLK>;
44 resets = <&cru SRST_CORE1>;
54 resets = <&cru SRST_CORE2>;
64 resets = <&cru SRST_CORE3>;
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
[all …]
Drk3xxx.dtsi42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
44 assigned-clocks = <&cru ACLK_GPU>;
46 resets = <&cru SRST_GPU>;
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
78 clocks = <&cru CORE_PERI>;
92 clocks = <&cru CORE_PERI>;
110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
169 clocks = <&cru HCLK_OTG0>;
[all …]
Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
36 clocks = <&cru ARMCLK>;
68 clocks = <&cru ACLK_LCDC0>,
69 <&cru DCLK_LCDC0>,
70 <&cru HCLK_LCDC0>;
73 resets = <&cru SRST_LCDC0_AXI>,
74 <&cru SRST_LCDC0_AHB>,
75 <&cru SRST_LCDC0_DCLK>;
94 clocks = <&cru ACLK_LCDC1>,
95 <&cru DCLK_LCDC1>,
[all …]
Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
41 resets = <&cru SRST_CORE0>;
47 clocks = <&cru ARMCLK>;
54 resets = <&cru SRST_CORE1>;
111 assigned-clocks = <&cru SCLK_GPU>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
116 resets = <&cru SRST_GPU>;
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
[all …]
Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
200 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
[all …]
Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
27 clocks = <&cru ARMCLK>;
29 resets = <&cru SRST_CORE0>;
37 resets = <&cru SRST_CORE1>;
45 resets = <&cru SRST_CORE2>;
53 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
43 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44 <&cru SCLK_UPHY0_TCPDPHY_REF>;
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
48 resets = <&cru SRST_UPHY0>,
49 <&cru SRST_UPHY0_PIPE_L00>,
50 <&cru SRST_P_UPHY0_TCPHY>;
67 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68 <&cru SCLK_UPHY1_TCPDPHY_REF>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Drockchip-pcie-ep.txt45 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
53 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
Drockchip-pcie-host.txt85 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
86 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
94 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
104 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
105 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
106 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Drockchip,rk3188-cru.yaml4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
36 - rockchip,rk3066a-cru
37 - rockchip,rk3188-cru
38 - rockchip,rk3188a-cru
72 cru: clock-controller@20000000 {
73 compatible = "rockchip,rk3188-cru";
Drockchip,px30-cru.yaml4 $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
7 title: Rockchip PX30 Clock and Reset Unit (CRU)
19 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
33 - rockchip,px30-cru
48 - description: Clock for both PMUCRU and CRU
49 - description: Clock for CRU (sourced from PMUCRU)
77 const: rockchip,px30-cru
99 #include <dt-bindings/clock/px30-cru.h>
111 cru: clock-controller@ff2b0000 {
112 compatible = "rockchip,px30-cru";
Drockchip,rk3128-cru.yaml4 $id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
7 title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)
19 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
26 - rockchip,rk3126-cru
27 - rockchip,rk3128-cru
70 cru: clock-controller@20000000 {
71 compatible = "rockchip,rk3128-cru";
/Linux-v6.1/Documentation/devicetree/bindings/net/
Drockchip-dwmac.yaml114 #include <dt-bindings/clock/rk3288-cru.h>
121 clocks = <&cru SCLK_MAC>,
122 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
123 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
124 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
129 assigned-clocks = <&cru SCLK_MAC>;
/Linux-v6.1/Documentation/devicetree/bindings/media/
Drockchip-rga.yaml67 #include <dt-bindings/clock/rk3399-cru.h>
74 clocks = <&cru ACLK_RGA>,
75 <&cru HCLK_RGA>,
76 <&cru SCLK_RGA_CORE>;
79 resets = <&cru SRST_RGA_CORE>,
80 <&cru SRST_A_RGA>,
81 <&cru SRST_H_RGA>;
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dbrcm,cru.yaml4 $id: http://devicetree.org/schemas/mfd/brcm,cru.yaml#
7 title: Broadcom CRU
13 Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware
21 - brcm,ns-cru
25 description: CRU registers
59 cru-bus@1800c100 {
60 compatible = "brcm,ns-cru", "simple-mfd";
93 compatible = "brcm,cru-clkset", "syscon";
/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Dsnps,dwcmshc-sdhci.yaml68 clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
79 clocks = <&cru 17>, <&cru 18>;
/Linux-v6.1/Documentation/devicetree/bindings/power/
Drockchip,power-controller.yaml154 #include <dt-bindings/clock/rk3399-cru.h>
209 clocks = <&cru ACLK_IEP>,
210 <&cru HCLK_IEP>;
216 clocks = <&cru ACLK_RGA>,
217 <&cru HCLK_RGA>;
224 clocks = <&cru ACLK_VCODEC>,
225 <&cru HCLK_VCODEC>;
231 clocks = <&cru ACLK_VDU>,
232 <&cru HCLK_VDU>;
245 clocks = <&cru ACLK_HDCP>,
[all …]

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