Lines Matching full:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG0>;
293 resets = <&cru SRST_USB3OTG0>;
302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303 <&cru ACLK_USB3OTG1>;
311 resets = <&cru SRST_USB3OTG1>;
332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
333 <&cru PCLK_USB>;
343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
344 <&cru PCLK_USB>;
354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
355 <&cru PCLK_USB>;
365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
366 <&cru PCLK_USB>;
418 cru: clock-controller@fdd20000 { label
419 compatible = "rockchip,rk3568-cru";
425 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
514 clocks = <&cru ACLK_GPU_PRE>,
515 <&cru PCLK_GPU_PRE>;
523 clocks = <&cru HCLK_VI>,
524 <&cru PCLK_VI>;
533 clocks = <&cru HCLK_VO>,
534 <&cru PCLK_VO>,
535 <&cru ACLK_VOP_PRE>;
544 clocks = <&cru HCLK_RGA_PRE>,
545 <&cru PCLK_RGA_PRE>;
557 clocks = <&cru HCLK_VPU_PRE>;
563 clocks = <&cru HCLK_RKVDEC_PRE>;
571 clocks = <&cru HCLK_RKVENC_PRE>;
587 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
599 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
610 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
619 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
629 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
639 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
640 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
644 resets = <&cru SRST_SDMMC2>;
655 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
656 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
657 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
658 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
663 resets = <&cru SRST_A_GMAC1>;
700 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
701 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
736 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
747 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
752 resets = <&cru SRST_P_DSITX_0>;
775 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
780 resets = <&cru SRST_P_DSITX_1>;
802 clocks = <&cru PCLK_HDMI_HOST>,
803 <&cru CLK_HDMI_SFR>,
804 <&cru CLK_HDMI_CEC>,
806 <&cru HCLK_VO>;
963 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
964 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
965 <&cru CLK_PCIE20_AUX_NDFT>;
985 resets = <&cru SRST_PCIE20_POWERUP>;
1004 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1005 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1009 resets = <&cru SRST_SDMMC0>;
1018 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1019 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1023 resets = <&cru SRST_SDMMC1>;
1032 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1043 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1045 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1046 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1047 <&cru TCLK_EMMC>;
1057 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1072 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1076 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1087 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1089 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1090 <&cru HCLK_I2S1_8CH>;
1094 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1112 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1113 <&cru HCLK_I2S3_2CH>;
1117 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1128 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1139 resets = <&cru SRST_M_PDM>;
1151 clocks = <&cru ACLK_BUS>;
1162 clocks = <&cru ACLK_BUS>;
1171 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1184 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1197 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1210 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1223 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1236 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1244 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1259 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1274 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1289 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1304 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1318 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1332 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1346 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1360 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1374 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1388 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1402 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1416 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1501 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1503 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1505 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1506 <&cru SRST_TSADCPHY>;
1521 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1523 resets = <&cru SRST_P_SARADC>;
1532 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1543 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1554 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1565 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1576 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1587 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1598 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1609 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1620 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1631 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1642 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1653 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1665 <&cru PCLK_PIPEPHY1>,
1666 <&cru PCLK_PIPE>;
1670 resets = <&cru SRST_PIPEPHY1>;
1681 <&cru PCLK_PIPEPHY2>,
1682 <&cru PCLK_PIPE>;
1686 resets = <&cru SRST_PIPEPHY2>;
1696 clocks = <&cru PCLK_MIPICSIPHY>;
1699 resets = <&cru SRST_P_MIPICSIPHY>;
1709 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1713 resets = <&cru SRST_P_MIPIDSIPHY0>;
1721 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1725 resets = <&cru SRST_P_MIPIDSIPHY1>;
1796 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1807 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1818 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1829 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;