Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
141 clocks = <&cru ARMCLKB>;
185 clocks = <&cru SCLK_DDRC>;
232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
256 <&cru SRST_A_PCIE>;
273 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
274 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
275 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
276 <&cru PCLK_GMAC>;
282 resets = <&cru SRST_A_GMAC>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
300 resets = <&cru SRST_SDIO0>;
311 assigned-clocks = <&cru HCLK_SD>;
313 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
314 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
318 resets = <&cru SRST_SDMMC>;
328 assigned-clocks = <&cru SCLK_EMMC>;
330 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
345 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
367 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
388 clocks = <&cru PCLK_COREDBG_L>;
396 clocks = <&cru PCLK_COREDBG_L>;
404 clocks = <&cru PCLK_COREDBG_L>;
412 clocks = <&cru PCLK_COREDBG_L>;
420 clocks = <&cru PCLK_COREDBG_B>;
428 clocks = <&cru PCLK_COREDBG_B>;
438 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
439 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
440 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
444 resets = <&cru SRST_A_USB3_OTG0>;
452 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
453 <&cru SCLK_USB3OTG0_SUSPEND>;
474 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
475 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
476 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
480 resets = <&cru SRST_A_USB3_OTG1>;
488 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
489 <&cru SCLK_USB3OTG1_SUSPEND>;
509 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
511 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
512 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
516 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
517 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
578 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
580 resets = <&cru SRST_P_SARADC>;
588 assigned-clocks = <&cru SCLK_I2C1>;
590 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
603 assigned-clocks = <&cru SCLK_I2C2>;
605 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
618 assigned-clocks = <&cru SCLK_I2C3>;
620 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
633 assigned-clocks = <&cru SCLK_I2C5>;
635 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
648 assigned-clocks = <&cru SCLK_I2C6>;
650 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
663 assigned-clocks = <&cru SCLK_I2C7>;
665 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
678 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
691 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
704 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
717 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
730 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
745 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
760 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
775 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
790 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
881 assigned-clocks = <&cru SCLK_TSADC>;
883 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
885 resets = <&cru SRST_TSADC>;
1042 clocks = <&cru ACLK_IEP>,
1043 <&cru HCLK_IEP>;
1049 clocks = <&cru ACLK_RGA>,
1050 <&cru HCLK_RGA>;
1057 clocks = <&cru ACLK_VCODEC>,
1058 <&cru HCLK_VCODEC>;
1064 clocks = <&cru ACLK_VDU>,
1065 <&cru HCLK_VDU>;
1074 clocks = <&cru ACLK_GPU>;
1082 clocks = <&cru PCLK_EDP_CTRL>;
1087 clocks = <&cru ACLK_EMMC>;
1093 clocks = <&cru ACLK_GMAC>,
1094 <&cru PCLK_GMAC>;
1100 clocks = <&cru HCLK_SDMMC>,
1101 <&cru SCLK_SDMMC>;
1107 clocks = <&cru HCLK_SDIO>;
1113 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1114 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1119 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1120 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1125 clocks = <&cru ACLK_USB3>;
1138 clocks = <&cru ACLK_HDCP>,
1139 <&cru HCLK_HDCP>,
1140 <&cru PCLK_HDCP>;
1146 clocks = <&cru ACLK_ISP0>,
1147 <&cru HCLK_ISP0>;
1154 clocks = <&cru ACLK_ISP1>,
1155 <&cru HCLK_ISP1>;
1168 clocks = <&cru ACLK_VOP0>,
1169 <&cru HCLK_VOP0>;
1176 clocks = <&cru ACLK_VOP1>,
1177 <&cru HCLK_VOP1>;
1312 clocks = <&cru PCLK_DDR_MON>;
1323 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1333 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1343 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1344 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1354 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1364 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1374 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1376 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1386 clocks = <&cru PCLK_EFUSE1024NS>;
1420 clocks = <&cru ACLK_DMAC0_PERILP>;
1431 clocks = <&cru ACLK_DMAC1_PERILP>;
1447 cru: clock-controller@ff760000 { label
1448 compatible = "rockchip,rk3399-cru";
1456 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1457 <&cru PLL_NPLL>,
1458 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1459 <&cru PCLK_PERIHP>,
1460 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1461 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1462 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1463 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1464 <&cru ACLK_GIC_PRE>,
1465 <&cru PCLK_DDR>,
1466 <&cru ACLK_VDU>;
1494 clocks = <&cru SCLK_MIPIDPHY_REF>,
1495 <&cru SCLK_DPHY_RX0_CFG>,
1496 <&cru PCLK_VIO_GRF>;
1506 clocks = <&cru SCLK_USB2PHY0_REF>;
1533 clocks = <&cru SCLK_USB2PHY1_REF>;
1569 clocks = <&cru SCLK_PCIEPHY_REF>;
1572 resets = <&cru SRST_PCIEPHY>;
1581 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1582 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1584 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1587 resets = <&cru SRST_UPHY0>,
1588 <&cru SRST_UPHY0_PIPE_L00>,
1589 <&cru SRST_P_UPHY0_TCPHY>;
1606 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1607 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1609 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1612 resets = <&cru SRST_UPHY1>,
1613 <&cru SRST_UPHY1_PIPE_L00>,
1614 <&cru SRST_P_UPHY1_TCPHY>;
1631 clocks = <&cru PCLK_WDT>;
1639 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1650 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1666 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1682 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1697 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1707 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1709 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1713 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1752 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1763 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1765 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1769 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1808 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1819 clocks = <&cru SCLK_ISP0>,
1820 <&cru ACLK_ISP0_WRAPPER>,
1821 <&cru HCLK_ISP0_WRAPPER>;
1845 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1856 clocks = <&cru SCLK_ISP1>,
1857 <&cru ACLK_ISP1_WRAPPER>,
1858 <&cru HCLK_ISP1_WRAPPER>;
1882 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1908 clocks = <&cru PCLK_HDMI_CTRL>,
1909 <&cru SCLK_HDMI_SFR>,
1910 <&cru SCLK_HDMI_CEC>,
1911 <&cru PCLK_VIO_GRF>,
1912 <&cru PLL_VPLL>;
1941 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1942 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1945 resets = <&cru SRST_P_MIPI_DSI0>;
1977 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1978 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1981 resets = <&cru SRST_P_MIPI_DSI1>;
2015 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2020 resets = <&cru SRST_P_EDP_CTRL>;
2053 clocks = <&cru ACLK_GPU>;
2096 clocks = <&cru PCLK_GPIO2>;
2109 clocks = <&cru PCLK_GPIO3>;
2122 clocks = <&cru PCLK_GPIO4>;