Lines Matching full:cru
7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
217 resets = <&cru SRST_MMC0>;
225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
231 resets = <&cru SRST_SDIO0>;
239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
245 resets = <&cru SRST_SDIO1>;
253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
259 resets = <&cru SRST_EMMC>;
269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
271 resets = <&cru SRST_SARADC>;
278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
328 clocks = <&cru PCLK_I2C1>;
341 clocks = <&cru PCLK_I2C3>;
354 clocks = <&cru PCLK_I2C4>;
367 clocks = <&cru PCLK_I2C5>;
379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
454 clocks = <&cru ACLK_DMAC2>;
543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
545 resets = <&cru SRST_TSADC>;
564 clocks = <&cru SCLK_MAC>,
565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
572 resets = <&cru SRST_MAC>;
581 clocks = <&cru HCLK_USBHOST0>;
592 clocks = <&cru HCLK_USBHOST0>;
603 clocks = <&cru HCLK_USBHOST1>;
617 clocks = <&cru HCLK_OTG0>;
632 clocks = <&cru HCLK_HSIC>;
644 clocks = <&cru ACLK_DMAC1>;
656 clocks = <&cru PCLK_I2C0>;
669 clocks = <&cru PCLK_I2C2>;
681 clocks = <&cru PCLK_RKPWM>;
691 clocks = <&cru PCLK_RKPWM>;
701 clocks = <&cru PCLK_RKPWM>;
711 clocks = <&cru PCLK_RKPWM>;
742 assigned-clocks = <&cru SCLK_EDP_24M>;
770 clocks = <&cru ACLK_IEP>,
771 <&cru ACLK_ISP>,
772 <&cru ACLK_RGA>,
773 <&cru ACLK_VIP>,
774 <&cru ACLK_VOP0>,
775 <&cru ACLK_VOP1>,
776 <&cru DCLK_VOP0>,
777 <&cru DCLK_VOP1>,
778 <&cru HCLK_IEP>,
779 <&cru HCLK_ISP>,
780 <&cru HCLK_RGA>,
781 <&cru HCLK_VIP>,
782 <&cru HCLK_VOP0>,
783 <&cru HCLK_VOP1>,
784 <&cru PCLK_EDP_CTRL>,
785 <&cru PCLK_HDMI_CTRL>,
786 <&cru PCLK_LVDS_PHY>,
787 <&cru PCLK_MIPI_CSI>,
788 <&cru PCLK_MIPI_DSI0>,
789 <&cru PCLK_MIPI_DSI1>,
790 <&cru SCLK_EDP_24M>,
791 <&cru SCLK_EDP>,
792 <&cru SCLK_ISP_JPE>,
793 <&cru SCLK_ISP>,
794 <&cru SCLK_RGA>;
813 clocks = <&cru ACLK_HEVC>,
814 <&cru SCLK_HEVC_CABAC>,
815 <&cru SCLK_HEVC_CORE>;
828 clocks = <&cru ACLK_VCODEC>,
829 <&cru HCLK_VCODEC>;
840 clocks = <&cru ACLK_GPU>;
862 cru: clock-controller@ff760000 { label
863 compatible = "rockchip,rk3288-cru";
870 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
871 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
872 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
873 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
874 <&cru PCLK_PERI>;
888 clocks = <&cru SCLK_EDP_24M>;
908 clocks = <&cru SCLK_OTGPHY0>;
911 resets = <&cru SRST_USBOTG_PHY>;
918 clocks = <&cru SCLK_OTGPHY1>;
921 resets = <&cru SRST_USBHOST0_PHY>;
928 clocks = <&cru SCLK_OTGPHY2>;
931 resets = <&cru SRST_USBHOST1_PHY>;
940 clocks = <&cru PCLK_WDT>;
949 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
965 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
980 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
981 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
983 resets = <&cru SRST_CRYPTO>;
991 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1001 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1015 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1023 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1026 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1061 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1072 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1075 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1110 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1121 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1146 clocks = <&cru PCLK_LVDS_PHY>;
1180 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1184 resets = <&cru SRST_EDP>;
1215 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1242 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1252 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1262 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1275 clocks = <&cru ACLK_GPU>;
1385 clocks = <&cru ACLK_DMAC1>;
1394 clocks = <&cru PCLK_EFUSE256>;
1430 clocks = <&cru PCLK_GPIO0>;
1443 clocks = <&cru PCLK_GPIO1>;
1456 clocks = <&cru PCLK_GPIO2>;
1469 clocks = <&cru PCLK_GPIO3>;
1482 clocks = <&cru PCLK_GPIO4>;
1495 clocks = <&cru PCLK_GPIO5>;
1508 clocks = <&cru PCLK_GPIO6>;
1521 clocks = <&cru PCLK_GPIO7>;
1534 clocks = <&cru PCLK_GPIO8>;