Lines Matching full:cru
9 #include <dt-bindings/clock/rk3066a-cru.h>
36 clocks = <&cru ARMCLK>;
68 clocks = <&cru ACLK_LCDC0>,
69 <&cru DCLK_LCDC0>,
70 <&cru HCLK_LCDC0>;
73 resets = <&cru SRST_LCDC0_AXI>,
74 <&cru SRST_LCDC0_AHB>,
75 <&cru SRST_LCDC0_DCLK>;
94 clocks = <&cru ACLK_LCDC1>,
95 <&cru DCLK_LCDC1>,
96 <&cru HCLK_LCDC1>;
99 resets = <&cru SRST_LCDC1_AXI>,
100 <&cru SRST_LCDC1_AHB>,
101 <&cru SRST_LCDC1_DCLK>;
120 clocks = <&cru HCLK_HDMI>;
160 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
176 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
192 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
202 cru: clock-controller@20000000 { label
203 compatible = "rockchip,rk3066a-cru";
210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
211 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
212 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
213 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
224 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
233 clocks = <&cru PCLK_EFUSE>;
245 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
253 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
260 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
264 resets = <&cru SRST_TSADC>;
280 clocks = <&cru PCLK_GPIO0>;
293 clocks = <&cru PCLK_GPIO1>;
306 clocks = <&cru PCLK_GPIO2>;
319 clocks = <&cru PCLK_GPIO3>;
332 clocks = <&cru PCLK_GPIO4>;
345 clocks = <&cru PCLK_GPIO6>;
692 clocks = <&cru SCLK_OTGPHY0>;
700 clocks = <&cru SCLK_OTGPHY1>;
763 clocks = <&cru ACLK_LCDC0>,
764 <&cru ACLK_LCDC1>,
765 <&cru DCLK_LCDC0>,
766 <&cru DCLK_LCDC1>,
767 <&cru HCLK_LCDC0>,
768 <&cru HCLK_LCDC1>,
769 <&cru SCLK_CIF1>,
770 <&cru ACLK_CIF1>,
771 <&cru HCLK_CIF1>,
772 <&cru SCLK_CIF0>,
773 <&cru ACLK_CIF0>,
774 <&cru HCLK_CIF0>,
775 <&cru HCLK_HDMI>,
776 <&cru ACLK_IPP>,
777 <&cru HCLK_IPP>,
778 <&cru ACLK_RGA>,
779 <&cru HCLK_RGA>;
791 clocks = <&cru ACLK_VDPU>,
792 <&cru ACLK_VEPU>,
793 <&cru HCLK_VDPU>,
794 <&cru HCLK_VEPU>;
801 clocks = <&cru ACLK_GPU>;