Home
last modified time | relevance | path

Searched +full:clk +full:- +full:mgr (Results 1 – 25 of 27) sorted by relevance

12

/Linux-v5.10/drivers/fpga/
Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
[all …]
Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
7 #include <linux/clk.h>
10 #include <linux/fpga/fpga-mgr.h>
65 * struct a10_fpga_priv - private data for fpga manager
68 * @clk: clock
73 struct clk *clk; member
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
17 - const: altr,clk-mgr
22 - compatible
27 - |
29 compatible = "altr,clk-mgr";
/Linux-v5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dvenc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
249 struct clk *tv_dac_clk;
273 venc_write_reg(VENC_LLEN, config->llen); in venc_write_config()
274 venc_write_reg(VENC_FLENS, config->flens); in venc_write_config()
275 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); in venc_write_config()
276 venc_write_reg(VENC_C_PHASE, config->c_phase); in venc_write_config()
277 venc_write_reg(VENC_GAIN_U, config->gain_u); in venc_write_config()
278 venc_write_reg(VENC_GAIN_V, config->gain_v); in venc_write_config()
279 venc_write_reg(VENC_GAIN_Y, config->gain_y); in venc_write_config()
[all …]
Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
152 struct clk *clkin;
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
[all …]
Ddpi.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/clk.h>
55 /* only used in non-DT mode */
58 return dev_get_drvdata(&pdev->dev); in dpi_get_data_from_pdev()
155 if (ctx->pck_min >= 100000000) { in dpi_calc_dispc_cb()
163 ctx->dispc_cinfo.lck_div = lckd; in dpi_calc_dispc_cb()
164 ctx->dispc_cinfo.pck_div = pckd; in dpi_calc_dispc_cb()
165 ctx->dispc_cinfo.lck = lck; in dpi_calc_dispc_cb()
166 ctx->dispc_cinfo.pck = pck; in dpi_calc_dispc_cb()
182 if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) in dpi_calc_hsdiv_cb()
[all …]
Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/clk.h>
26 #include <sound/omap-hdmi-audio.h>
41 r = pm_runtime_get_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
43 pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
56 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
57 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
98 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
101 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
[all …]
Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <linux/clk.h>
31 #include <sound/omap-hdmi-audio.h>
45 r = pm_runtime_get_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
47 pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
60 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
61 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
117 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
165 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
174 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
[all …]
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk.h>
206 struct omap_overlay_manager *mgr);
208 struct omap_overlay_manager *mgr);
302 struct clk *dss_clk;
402 return dev_get_drvdata(&dsidev->dev); in dsi_get_dsidrv_data()
407 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
428 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
438 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
439 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/Linux-v5.10/drivers/clk/socfpga/
Dclk-gate-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include "clk.h"
27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
[all …]
Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
15 #include "clk.h"
96 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()
97 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()
98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
[all …]
Dclk-pll-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include "clk.h"
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
66 static struct clk * __init __socfpga_pll_init(struct device_node *node, in __socfpga_pll_init()
70 struct clk *clk; in __socfpga_pll_init() local
72 const char *clk_name = node->name; in __socfpga_pll_init()
85 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; in __socfpga_pll_init()
[all …]
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
14 #include "clk.h"
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
73 static __init struct clk *__socfpga_pll_init(struct device_node *node, in __socfpga_pll_init()
77 struct clk *clk; in __socfpga_pll_init() local
[all …]
/Linux-v5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/Linux-v5.10/include/video/
Domapfb_dss.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
88 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
91 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
92 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
93 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
94 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
99 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
100 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
101 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
102 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
34 /* functions shared with other clk mgr */
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
37 /* functions shared with other clk mgr*/
/Linux-v5.10/drivers/slimbus/
Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
14 #include <linux/clk.h>
88 /* Resource group info for manager, and non-ported generic device-components */
116 struct clk *rclk;
117 struct clk *hclk;
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
[all …]
/Linux-v5.10/drivers/misc/habanalabs/common/
Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2019 HabanaLabs, Ltd.
18 #include <linux/dma-direction.h>
26 * bits[63:62] - Encode mmap type
27 * bits[45:0] - mmap offset value
32 #define HL_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT)
76 #define IS_POWER_OF_2(n) (n != 0 && ((n & (n - 1)) == 0))
84 * struct pgt_info - MMU hop page info.
85 * @node: hash linked-list node for the pgts shadow hash of pgts.
108 * enum hl_pci_match_mode - pci match mode per region
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
103 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
106 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
109 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
112 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
115 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
118 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
445 return &opp->base; in dce120_opp_create()
462 ctx->dc->caps.extended_aux_timeout_support); in dce120_aux_engine_create()
464 return &aux_engine->base; in dce120_aux_engine_create()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c40 dc->ctx->logger
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
74 /* default DCF CLK DPM on RV*/
80 /* default DISP CLK voltage state on RV */
86 /* default DPP CLK voltage state on RV */
92 /* default PHY CLK voltage state on RV */
304 input->src.is_hsplit = false; in pipe_ctx_to_e2e_pipe_params()
307 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
[all …]

12