Lines Matching +full:clk +full:- +full:mgr
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
22 compatible = "shared-dma-pool";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
63 compatible = "arm,armv8-pmuv3";
68 interrupt-affinity = <&cpu0>,
72 interrupt-parent = <&intc>;
76 compatible = "arm,psci-0.2";
80 intc: interrupt-controller@fffc1000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
95 interrupt-parent = <&intc>;
99 #address-cells = <0x1>;
100 #size-cells = <0x1>;
102 compatible = "fpga-region";
103 fpga-mgr = <&fpga_mgr>;
106 clkmgr: clock-controller@ffd10000 {
107 compatible = "intel,stratix10-clkmgr";
109 #clock-cells = <1>;
113 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
118 cb_intosc_ls_clk: cb-intosc-ls-clk {
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
123 f2s_free_clk: f2s-free-clk {
124 #clock-cells = <0>;
125 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 compatible = "fixed-clock";
133 qspi_clk: qspi-clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <200000000>;
141 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
144 interrupt-names = "macirq";
145 mac-address = [00 00 00 00 00 00];
147 reset-names = "stmmaceth", "stmmaceth-ocp";
149 clock-names = "stmmaceth", "ptp_ref";
150 tx-fifo-depth = <16384>;
151 rx-fifo-depth = <16384>;
152 snps,multicast-filter-bins = <256>;
154 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
159 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
162 interrupt-names = "macirq";
163 mac-address = [00 00 00 00 00 00];
165 reset-names = "stmmaceth", "stmmaceth-ocp";
167 clock-names = "stmmaceth", "ptp_ref";
168 tx-fifo-depth = <16384>;
169 rx-fifo-depth = <16384>;
170 snps,multicast-filter-bins = <256>;
172 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
177 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
180 interrupt-names = "macirq";
181 mac-address = [00 00 00 00 00 00];
183 reset-names = "stmmaceth", "stmmaceth-ocp";
185 clock-names = "stmmaceth", "ptp_ref";
186 tx-fifo-depth = <16384>;
187 rx-fifo-depth = <16384>;
188 snps,multicast-filter-bins = <256>;
190 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "snps,dw-apb-gpio";
202 porta: gpio-controller@0 {
203 compatible = "snps,dw-apb-gpio-port";
204 gpio-controller;
205 #gpio-cells = <2>;
206 snps,nr-gpios = <24>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "snps,dw-apb-gpio";
222 portb: gpio-controller@0 {
223 compatible = "snps,dw-apb-gpio-port";
224 gpio-controller;
225 #gpio-cells = <2>;
226 snps,nr-gpios = <24>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "snps,designware-i2c";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "snps,designware-i2c";
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "snps,designware-i2c";
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "snps,designware-i2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "snps,designware-i2c";
290 #address-cells = <1>;
291 #size-cells = <0>;
292 compatible = "altr,socfpga-dw-mshc";
295 fifo-depth = <0x400>;
297 reset-names = "reset";
300 clock-names = "biu", "ciu";
305 nand: nand-controller@ffb90000 {
306 #address-cells = <1>;
307 #size-cells = <0>;
308 compatible = "altr,socfpga-denali-nand";
311 reg-names = "nand_data", "denali_reg";
316 clock-names = "nand", "nand_x", "ecc";
322 compatible = "mmio-sram";
338 #dma-cells = <1>;
339 #dma-channels = <8>;
340 #dma-requests = <32>;
342 clock-names = "apb_pclk";
344 reset-names = "dma", "dma-ocp";
348 #reset-cells = <1>;
349 compatible = "altr,stratix10-rst-mgr";
354 compatible = "arm,mmu-500", "arm,smmu-v2";
356 #global-interrupts = <2>;
357 #iommu-cells = <1>;
359 clock-names = "iommu";
360 interrupt-parent = <&intc>;
362 <0 129 4>, /* Global Non-secure Fault */
363 /* Non-secure Context Interrupts (32) */
372 stream-match-mask = <0x7ff0>;
377 compatible = "snps,dw-apb-ssi";
378 #address-cells = <1>;
379 #size-cells = <0>;
383 reset-names = "spi";
384 reg-io-width = <4>;
385 num-cs = <4>;
391 compatible = "snps,dw-apb-ssi";
392 #address-cells = <1>;
393 #size-cells = <0>;
397 reset-names = "spi";
398 reg-io-width = <4>;
399 num-cs = <4>;
405 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
411 compatible = "arm,armv8-timer";
419 compatible = "snps,dw-apb-timer";
423 clock-names = "timer";
427 compatible = "snps,dw-apb-timer";
431 clock-names = "timer";
435 compatible = "snps,dw-apb-timer";
439 clock-names = "timer";
443 compatible = "snps,dw-apb-timer";
447 clock-names = "timer";
451 compatible = "snps,dw-apb-uart";
454 reg-shift = <2>;
455 reg-io-width = <4>;
462 compatible = "snps,dw-apb-uart";
465 reg-shift = <2>;
466 reg-io-width = <4>;
473 #phy-cells = <0>;
474 compatible = "usb-nop-xceiv";
483 phy-names = "usb2-phy";
485 reset-names = "dwc2", "dwc2-ecc";
496 phy-names = "usb2-phy";
498 reset-names = "dwc2", "dwc2-ecc";
505 compatible = "snps,dw-wdt";
514 compatible = "snps,dw-wdt";
523 compatible = "snps,dw-wdt";
532 compatible = "snps,dw-wdt";
541 compatible = "altr,sdr-ctl", "syscon";
546 compatible = "altr,socfpga-s10-ecc-manager",
547 "altr,socfpga-a10-ecc-manager";
548 altr,sysmgr-syscon = <&sysmgr>;
549 #address-cells = <1>;
550 #size-cells = <1>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 compatible = "altr,sdram-edac-s10";
558 altr,sdr-syscon = <&sdr>;
562 ocram-ecc@ff8cc000 {
563 compatible = "altr,socfpga-s10-ocram-ecc",
564 "altr,socfpga-a10-ocram-ecc";
566 altr,ecc-parent = <&ocram>;
570 usb0-ecc@ff8c4000 {
571 compatible = "altr,socfpga-s10-usb-ecc",
572 "altr,socfpga-usb-ecc";
574 altr,ecc-parent = <&usb0>;
578 emac0-rx-ecc@ff8c0000 {
579 compatible = "altr,socfpga-s10-eth-mac-ecc",
580 "altr,socfpga-eth-mac-ecc";
582 altr,ecc-parent = <&gmac0>;
586 emac0-tx-ecc@ff8c0400 {
587 compatible = "altr,socfpga-s10-eth-mac-ecc",
588 "altr,socfpga-eth-mac-ecc";
590 altr,ecc-parent = <&gmac0>;
597 compatible = "cdns,qspi-nor";
598 #address-cells = <1>;
599 #size-cells = <0>;
603 cdns,fifo-depth = <128>;
604 cdns,fifo-width = <4>;
605 cdns,trigger-address = <0x00000000>;
613 compatible = "intel,stratix10-svc";
615 memory-region = <&service_reserved>;
617 fpga_mgr: fpga-mgr {
618 compatible = "intel,stratix10-soc-fpga-mgr";