1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include "clk.h"
27 	if (socfpgaclk->fixed_div)  in socfpga_gate_clk_recalc_rate()
28 		div = socfpgaclk->fixed_div;  in socfpga_gate_clk_recalc_rate()
29 	else if (socfpgaclk->div_reg) {  in socfpga_gate_clk_recalc_rate()
30 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_gate_clk_recalc_rate()
31 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_gate_clk_recalc_rate()
45 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {  in socfpga_clk_prepare()
47 			switch (socfpgaclk->clk_phase[i]) {  in socfpga_clk_prepare()
79 		if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))  in socfpga_clk_prepare()
80 			regmap_write(socfpgaclk->sys_mgr_base_addr,  in socfpga_clk_prepare()
101 	struct clk *clk;  in __socfpga_gate_init()  local
103 	const char *clk_name = node->name;  in __socfpga_gate_init()
112 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);  in __socfpga_gate_init()
117 		socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];  in __socfpga_gate_init()
118 		socfpga_clk->hw.bit_idx = clk_gate[1];  in __socfpga_gate_init()
124 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in __socfpga_gate_init()
126 		socfpga_clk->fixed_div = 0;  in __socfpga_gate_init()
128 		socfpga_clk->fixed_div = fixed_div;  in __socfpga_gate_init()
130 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in __socfpga_gate_init()
132 		socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];  in __socfpga_gate_init()
133 		socfpga_clk->shift = div_reg[1];  in __socfpga_gate_init()
134 		socfpga_clk->width = div_reg[2];  in __socfpga_gate_init()
136 		socfpga_clk->div_reg = NULL;  in __socfpga_gate_init()
139 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);  in __socfpga_gate_init()
141 		socfpga_clk->clk_phase[0] = clk_phase[0];  in __socfpga_gate_init()
142 		socfpga_clk->clk_phase[1] = clk_phase[1];  in __socfpga_gate_init()
144 		socfpga_clk->sys_mgr_base_addr =  in __socfpga_gate_init()
145 			syscon_regmap_lookup_by_compatible("altr,sys-mgr");  in __socfpga_gate_init()
146 		if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {  in __socfpga_gate_init()
147 			pr_err("%s: failed to find altr,sys-mgr regmap!\n",  in __socfpga_gate_init()
153 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_gate_init()
161 	socfpga_clk->hw.hw.init = &init;  in __socfpga_gate_init()
163 	clk = clk_register(NULL, &socfpga_clk->hw.hw);  in __socfpga_gate_init()
164 	if (WARN_ON(IS_ERR(clk))) {  in __socfpga_gate_init()
168 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);  in __socfpga_gate_init()