1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  Copyright 2011-2012 Calxeda, Inc.
4  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6  * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
15 #include "clk.h"
96 	if (socfpgaclk->fixed_div)  in socfpga_clk_recalc_rate()
97 		div = socfpgaclk->fixed_div;  in socfpga_clk_recalc_rate()
98 	else if (socfpgaclk->div_reg) {  in socfpga_clk_recalc_rate()
99 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_clk_recalc_rate()
100 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_clk_recalc_rate()
102 		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)  in socfpga_clk_recalc_rate()
119 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {  in socfpga_clk_prepare()
120 		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");  in socfpga_clk_prepare()
122 			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);  in socfpga_clk_prepare()
123 			return -EINVAL;  in socfpga_clk_prepare()
127 			switch (socfpgaclk->clk_phase[i]) {  in socfpga_clk_prepare()
177 	struct clk *clk;  in socfpga_gate_init()  local
179 	const char *clk_name = node->name;  in socfpga_gate_init()
193 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);  in socfpga_gate_init()
198 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];  in socfpga_gate_init()
199 		socfpga_clk->hw.bit_idx = clk_gate[1];  in socfpga_gate_init()
201 		ops->enable = clk_gate_ops.enable;  in socfpga_gate_init()
202 		ops->disable = clk_gate_ops.disable;  in socfpga_gate_init()
205 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in socfpga_gate_init()
207 		socfpga_clk->fixed_div = 0;  in socfpga_gate_init()
209 		socfpga_clk->fixed_div = fixed_div;  in socfpga_gate_init()
211 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in socfpga_gate_init()
213 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];  in socfpga_gate_init()
214 		socfpga_clk->shift = div_reg[1];  in socfpga_gate_init()
215 		socfpga_clk->width = div_reg[2];  in socfpga_gate_init()
217 		socfpga_clk->div_reg = NULL;  in socfpga_gate_init()
220 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);  in socfpga_gate_init()
222 		socfpga_clk->clk_phase[0] = clk_phase[0];  in socfpga_gate_init()
223 		socfpga_clk->clk_phase[1] = clk_phase[1];  in socfpga_gate_init()
226 	of_property_read_string(node, "clock-output-names", &clk_name);  in socfpga_gate_init()
234 		ops->get_parent = NULL;  in socfpga_gate_init()
235 		ops->set_parent = NULL;  in socfpga_gate_init()
239 	socfpga_clk->hw.hw.init = &init;  in socfpga_gate_init()
241 	clk = clk_register(NULL, &socfpga_clk->hw.hw);  in socfpga_gate_init()
242 	if (WARN_ON(IS_ERR(clk))) {  in socfpga_gate_init()
246 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);  in socfpga_gate_init()