Lines Matching +full:clk +full:- +full:mgr
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
35 interrupt-controller;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "simple-bus";
45 interrupt-parent = <&intc>;
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
66 #dma-cells = <1>;
67 #dma-channels = <8>;
68 #dma-requests = <32>;
70 clock-names = "apb_pclk";
72 reset-names = "dma", "dma-ocp";
77 #address-cells = <0x1>;
78 #size-cells = <0x1>;
80 compatible = "fpga-region";
81 fpga-mgr = <&fpga_mgr>;
85 compatible = "altr,clk-mgr";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 #clock-cells = <0>;
116 compatible = "altr,socfpga-a10-pll-clock";
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-a10-perip-clk";
125 div-reg = <0x140 0 11>;
129 #clock-cells = <0>;
130 compatible = "altr,socfpga-a10-perip-clk";
132 div-reg = <0x144 0 11>;
136 #clock-cells = <0>;
137 compatible = "altr,socfpga-a10-perip-clk";
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-a10-perip-clk";
150 #clock-cells = <0>;
151 compatible = "altr,socfpga-a10-perip-clk";
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-a10-perip-clk";
164 #clock-cells = <0>;
165 compatible = "altr,socfpga-a10-perip-clk"
172 #clock-cells = <0>;
173 compatible = "altr,socfpga-a10-perip-clk";
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-a10-pll-clock";
210 #clock-cells = <0>;
211 compatible = "altr,socfpga-a10-perip-clk";
213 div-reg = <0x140 16 11>;
217 #clock-cells = <0>;
218 compatible = "altr,socfpga-a10-perip-clk";
220 div-reg = <0x144 16 11>;
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-perip-clk";
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
281 #clock-cells = <0>;
282 compatible = "altr,socfpga-a10-perip-clk";
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
313 fixed-divider = <4>;
318 #clock-cells = <0>;
319 compatible = "altr,socfpga-a10-perip-clk";
321 fixed-divider = <4>;
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-a10-gate-clk";
328 div-reg = <0xA8 0 2>;
329 clk-gate = <0x48 1>;
333 #clock-cells = <0>;
334 compatible = "altr,socfpga-a10-gate-clk";
336 div-reg = <0xA8 8 2>;
337 clk-gate = <0x48 2>;
341 #clock-cells = <0>;
342 compatible = "altr,socfpga-a10-gate-clk";
344 div-reg = <0xA8 16 2>;
345 clk-gate = <0x48 3>;
349 #clock-cells = <0>;
350 compatible = "altr,socfpga-a10-gate-clk";
352 fixed-divider = <4>;
353 clk-gate = <0x48 0>;
357 #clock-cells = <0>;
358 compatible = "altr,socfpga-a10-gate-clk";
360 clk-gate = <0xC8 5>;
361 clk-phase = <0 135>;
365 #clock-cells = <0>;
366 compatible = "altr,socfpga-a10-gate-clk";
368 clk-gate = <0xC8 11>;
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-a10-gate-clk";
375 clk-gate = <0xC8 10>;
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-a10-gate-clk";
382 clk-gate = <0xC8 10>;
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-a10-gate-clk";
389 fixed-divider = <4>;
390 clk-gate = <0xC8 10>;
394 #clock-cells = <0>;
395 compatible = "altr,socfpga-a10-gate-clk";
397 clk-gate = <0xC8 9>;
401 #clock-cells = <0>;
402 compatible = "altr,socfpga-a10-gate-clk";
404 clk-gate = <0xC8 8>;
408 #clock-cells = <0>;
409 compatible = "altr,socfpga-a10-gate-clk";
411 clk-gate = <0xC8 6>;
416 socfpga_axi_setup: stmmac-axi-config {
423 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
427 interrupt-names = "macirq";
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
435 clock-names = "stmmaceth", "ptp_ref";
437 reset-names = "stmmaceth", "stmmaceth-ocp";
438 snps,axi-config = <&socfpga_axi_setup>;
443 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
444 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
447 interrupt-names = "macirq";
449 mac-address = [00 00 00 00 00 00];
450 snps,multicast-filter-bins = <256>;
451 snps,perfect-filter-entries = <128>;
452 tx-fifo-depth = <4096>;
453 rx-fifo-depth = <16384>;
455 clock-names = "stmmaceth", "ptp_ref";
457 reset-names = "stmmaceth", "stmmaceth-ocp";
458 snps,axi-config = <&socfpga_axi_setup>;
463 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
464 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
467 interrupt-names = "macirq";
469 mac-address = [00 00 00 00 00 00];
470 snps,multicast-filter-bins = <256>;
471 snps,perfect-filter-entries = <128>;
472 tx-fifo-depth = <4096>;
473 rx-fifo-depth = <16384>;
475 clock-names = "stmmaceth", "ptp_ref";
477 reset-names = "stmmaceth", "stmmaceth-ocp";
478 snps,axi-config = <&socfpga_axi_setup>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 compatible = "snps,dw-apb-gpio";
490 porta: gpio-controller@0 {
491 compatible = "snps,dw-apb-gpio-port";
492 gpio-controller;
493 #gpio-cells = <2>;
494 snps,nr-gpios = <29>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "snps,dw-apb-gpio";
510 portb: gpio-controller@0 {
511 compatible = "snps,dw-apb-gpio-port";
512 gpio-controller;
513 #gpio-cells = <2>;
514 snps,nr-gpios = <29>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 compatible = "snps,dw-apb-gpio";
530 portc: gpio-controller@0 {
531 compatible = "snps,dw-apb-gpio-port";
532 gpio-controller;
533 #gpio-cells = <2>;
534 snps,nr-gpios = <27>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
542 fpga_mgr: fpga-mgr@ffd03000 {
543 compatible = "altr,socfpga-a10-fpga-mgr";
548 reset-names = "fpgamgr";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "snps,designware-i2c";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "snps,designware-i2c";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "snps,designware-i2c";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "snps,designware-i2c";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 compatible = "snps,designware-i2c";
607 compatible = "snps,dw-apb-ssi";
608 #address-cells = <1>;
609 #size-cells = <0>;
612 num-cs = <4>;
616 reset-names = "spi";
621 compatible = "snps,dw-apb-ssi";
622 #address-cells = <1>;
623 #size-cells = <0>;
626 num-cs = <4>;
628 tx-dma-channel = <&pdma 16>;
629 rx-dma-channel = <&pdma 17>;
632 reset-names = "spi";
637 compatible = "altr,sdr-ctl", "syscon";
641 L2: cache-controller@fffff000 {
642 compatible = "arm,pl310-cache";
645 cache-unified;
646 cache-level = <2>;
647 prefetch-data = <1>;
648 prefetch-instr = <1>;
649 arm,shared-override;
653 #address-cells = <1>;
654 #size-cells = <0>;
655 compatible = "altr,socfpga-dw-mshc";
658 fifo-depth = <0x400>;
660 clock-names = "biu", "ciu";
666 #address-cells = <1>;
667 #size-cells = <0>;
668 compatible = "altr,socfpga-denali-nand";
671 reg-names = "nand_data", "denali_reg";
674 clock-names = "nand", "nand_x", "ecc";
680 compatible = "mmio-sram";
685 compatible = "altr,socfpga-a10-ecc-manager";
686 altr,sysmgr-syscon = <&sysmgr>;
687 #address-cells = <1>;
688 #size-cells = <1>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
696 compatible = "altr,sdram-edac-a10";
697 altr,sdr-syscon = <&sdr>;
702 l2-ecc@ffd06010 {
703 compatible = "altr,socfpga-a10-l2-ecc";
709 ocram-ecc@ff8c3000 {
710 compatible = "altr,socfpga-a10-ocram-ecc";
716 emac0-rx-ecc@ff8c0800 {
717 compatible = "altr,socfpga-eth-mac-ecc";
719 altr,ecc-parent = <&gmac0>;
724 emac0-tx-ecc@ff8c0c00 {
725 compatible = "altr,socfpga-eth-mac-ecc";
727 altr,ecc-parent = <&gmac0>;
732 dma-ecc@ff8c8000 {
733 compatible = "altr,socfpga-dma-ecc";
735 altr,ecc-parent = <&pdma>;
740 usb0-ecc@ff8c8800 {
741 compatible = "altr,socfpga-usb-ecc";
743 altr,ecc-parent = <&usb0>;
750 compatible = "cdns,qspi-nor";
751 #address-cells = <1>;
752 #size-cells = <0>;
756 cdns,fifo-depth = <128>;
757 cdns,fifo-width = <4>;
758 cdns,trigger-address = <0x00000000>;
761 reset-names = "qspi", "qspi-ocp";
766 #reset-cells = <1>;
767 compatible = "altr,rst-mgr";
769 altr,modrst-offset = <0x20>;
772 scu: snoop-control-unit@ffffc000 {
773 compatible = "arm,cortex-a9-scu";
778 compatible = "altr,sys-mgr", "syscon";
780 cpu1-start-addr = <0xffd06230>;
785 compatible = "arm,cortex-a9-twd-timer";
792 compatible = "snps,dw-apb-timer";
796 clock-names = "timer";
798 reset-names = "timer";
802 compatible = "snps,dw-apb-timer";
806 clock-names = "timer";
808 reset-names = "timer";
812 compatible = "snps,dw-apb-timer";
816 clock-names = "timer";
818 reset-names = "timer";
822 compatible = "snps,dw-apb-timer";
826 clock-names = "timer";
828 reset-names = "timer";
832 compatible = "snps,dw-apb-uart";
835 reg-shift = <2>;
836 reg-io-width = <4>;
843 compatible = "snps,dw-apb-uart";
846 reg-shift = <2>;
847 reg-io-width = <4>;
854 #phy-cells = <0>;
855 compatible = "usb-nop-xceiv";
864 clock-names = "otg";
866 reset-names = "dwc2";
868 phy-names = "usb2-phy";
877 clock-names = "otg";
879 reset-names = "dwc2";
881 phy-names = "usb2-phy";
886 compatible = "snps,dw-wdt";
895 compatible = "snps,dw-wdt";