| /Linux-v5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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| /Linux-v5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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| D | k3-j7200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <1>;
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| D | k3-j721e.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <1>;
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| /Linux-v5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| /Linux-v5.10/arch/riscv/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group()
23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group()
33 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo()
34 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo()
35 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo()
46 return this_leaf ? this_leaf->size : 0; in get_cache_size()
53 return this_leaf ? (this_leaf->ways_of_associativity << 16 | in get_cache_geometry()
54 this_leaf->coherency_line_size) : in get_cache_geometry()
60 unsigned int sets, unsigned int line_size) in ci_leaf_init() argument
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /Linux-v5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /Linux-v5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| /Linux-v5.10/arch/mips/mm/ |
| D | c-octeon.c | 6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
36 * tagged cache. No flushing is needed
50 * Flush local I-cache for the specified range.
83 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
139 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
154 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_page()
179 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
180 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
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| D | sc-mips.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/cpu-type.h>
17 #include <asm/mips-cps.h>
21 * MIPS32/MIPS64 L2 cache handling
25 * Writeback and invalidate the secondary cache before DMA.
33 * Invalidate the secondary cache before DMA.
38 unsigned long almask = ~(lsize - 1); in mips_sc_inv()
41 cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); in mips_sc_inv()
47 /* L2 cache is permanently enabled */ in mips_sc_enable()
52 /* L2 cache is permanently enabled */ in mips_sc_disable()
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| D | c-r4k.c | 25 #include <asm/cache.h>
28 #include <asm/cpu-features.h>
29 #include <asm/cpu-type.h>
38 #include <asm/dma-coherence.h>
39 #include <asm/mips-cps.h>
42 * Bits describing what cache ops an SMP callback function may perform.
44 * R4K_HIT - Virtual user or kernel address based cache operations. The
47 * R4K_INDEX - Index based cache operations.
54 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
55 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
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| /Linux-v5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
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| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /Linux-v5.10/arch/sh/include/asm/ |
| D | cache.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
4 * include/asm-sh/cache.h
13 #include <cpu/cache.h>
21 unsigned int ways; /* Number of cache ways */
22 unsigned int sets; /* Number of cache sets */ member
23 unsigned int linesz; /* Cache line size (bytes) */
25 unsigned int way_size; /* sets * line size */
29 * in memory mapped cache array ops.
37 * 1. those used to select the cache set during indexing
|
| /Linux-v5.10/arch/mips/loongson64/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
75 val |= (irq - 1); in csr_ipi_write_action()
78 action &= ~BIT(irq - 1); in csr_ipi_write_action()
401 __cpu_number_map[i] = -1; in loongson3_smp_setup()
413 __cpu_logical_map[num] = -1; in loongson3_smp_setup()
474 return -EBUSY; in loongson3_cpu_disable()
510 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ in loongson3_type1_play_dead()
511 " cache 0, 1(%[addr]) \n" in loongson3_type1_play_dead()
512 " cache 0, 2(%[addr]) \n" in loongson3_type1_play_dead()
513 " cache 0, 3(%[addr]) \n" in loongson3_type1_play_dead()
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| /Linux-v5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
36 9: cache op, 0(t0) ; \
80 /* ZSC L2 Cache Register Access Register Definitions */
111 * Returns: v0 = i cache size, v1 = I cache line size
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
129 * the instruction cache:
131 * vi) 0x5 - 0x7: Reserved.
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| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #define populate_cache(cache, leaf, c_level, c_type) \ argument
10 leaf->type = c_type; \
11 leaf->level = c_level; \
12 leaf->coherency_line_size = c->cache.linesz; \
13 leaf->number_of_sets = c->cache.sets; \
14 leaf->ways_of_associativity = c->cache.ways; \
15 leaf->size = c->cache.linesz * c->cache.sets * \
16 c->cache.ways; \
27 * If Dcache is not set, we assume the cache structures in __init_cache_level()
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| /Linux-v5.10/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
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| /Linux-v5.10/arch/mips/cavium-octeon/executive/ |
| D | cvmx-l2c.c | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Implementation of the Level 2 Cache (L2C) control,
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43 * NOTE: This only protects calls from within a single application -
55 return -1; in cvmx_l2c_get_core_way_partition()
89 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; in cvmx_l2c_set_core_way_partition()
95 return -1; in cvmx_l2c_set_core_way_partition()
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