Lines Matching +full:cache +full:- +full:sets

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 	interrupt-parent = <&gic500>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
39 		#address-cells = <1>;
40 		#size-cells = <0>;
41 		cpu-map {
55 			compatible = "arm,cortex-a72";
58 			enable-method = "psci";
59 			i-cache-size = <0xC000>;
60 			i-cache-line-size = <64>;
61 			i-cache-sets = <256>;
62 			d-cache-size = <0x8000>;
63 			d-cache-line-size = <64>;
64 			d-cache-sets = <128>;
65 			next-level-cache = <&L2_0>;
69 			compatible = "arm,cortex-a72";
72 			enable-method = "psci";
73 			i-cache-size = <0xC000>;
74 			i-cache-line-size = <64>;
75 			i-cache-sets = <256>;
76 			d-cache-size = <0x8000>;
77 			d-cache-line-size = <64>;
78 			d-cache-sets = <128>;
79 			next-level-cache = <&L2_0>;
83 	L2_0: l2-cache0 {
84 		compatible = "cache";
85 		cache-level = <2>;
86 		cache-size = <0x100000>;
87 		cache-line-size = <64>;
88 		cache-sets = <2048>;
89 		next-level-cache = <&msmc_l3>;
92 	msmc_l3: l3-cache0 {
93 		compatible = "cache";
94 		cache-level = <3>;
99 			compatible = "linaro,optee-tz";
104 			compatible = "arm,psci-1.0";
109 	a72_timer0: timer-cl0-cpu0 {
110 		compatible = "arm,armv8-timer";
118 		compatible = "arm,armv8-pmuv3";
124 		compatible = "simple-bus";
125 		#address-cells = <2>;
126 		#size-cells = <2>;
162 			compatible = "simple-bus";
163 			#address-cells = <2>;
164 			#size-cells = <2>;
183 #include "k3-j721e-main.dtsi"
184 #include "k3-j721e-mcu-wakeup.dtsi"