Lines Matching +full:cache +full:- +full:sets
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
30 - sifive,rocket0
31 - sifive,e5
32 - sifive,e51
33 - sifive,u54-mc
34 - sifive,u54
35 - sifive,u5
36 - const: riscv
37 - const: riscv # Simulator only
39 Identifies that the hart uses the RISC-V instruction set
42 mmu-type:
45 hart. These values originate from the RISC-V Privileged
50 - riscv,sv32
51 - riscv,sv39
52 - riscv,sv48
56 Identifies the specific RISC-V instruction set architecture
57 supported by the hart. These are documented in the RISC-V
58 User-Level ISA document, available from
66 - rv64imac
67 - rv64imafdc
69 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
70 timebase-frequency: false
72 interrupt-controller:
77 '#interrupt-cells':
81 const: riscv,cpu-intc
83 interrupt-controller: true
86 - '#interrupt-cells'
87 - compatible
88 - interrupt-controller
91 - riscv,isa
92 - interrupt-controller
97 - |
100 #address-cells = <1>;
101 #size-cells = <0>;
102 timebase-frequency = <1000000>;
104 clock-frequency = <0>;
107 i-cache-block-size = <64>;
108 i-cache-sets = <128>;
109 i-cache-size = <16384>;
112 cpu_intc0: interrupt-controller {
113 #interrupt-cells = <1>;
114 compatible = "riscv,cpu-intc";
115 interrupt-controller;
119 clock-frequency = <0>;
121 d-cache-block-size = <64>;
122 d-cache-sets = <64>;
123 d-cache-size = <32768>;
124 d-tlb-sets = <1>;
125 d-tlb-size = <32>;
127 i-cache-block-size = <64>;
128 i-cache-sets = <64>;
129 i-cache-size = <32768>;
130 i-tlb-sets = <1>;
131 i-tlb-size = <32>;
132 mmu-type = "riscv,sv39";
135 tlb-split;
136 cpu_intc1: interrupt-controller {
137 #interrupt-cells = <1>;
138 compatible = "riscv,cpu-intc";
139 interrupt-controller;
144 - |
147 #address-cells = <1>;
148 #size-cells = <0>;
154 mmu-type = "riscv,sv48";
155 interrupt-controller {
156 #interrupt-cells = <1>;
157 interrupt-controller;
158 compatible = "riscv,cpu-intc";