Lines Matching +full:cache +full:- +full:sets

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 	interrupt-parent = <&gic500>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
38 		#address-cells = <1>;
39 		#size-cells = <0>;
40 		cpu-map {
54 			compatible = "arm,cortex-a72";
57 			enable-method = "psci";
58 			i-cache-size = <0xc000>;
59 			i-cache-line-size = <64>;
60 			i-cache-sets = <256>;
61 			d-cache-size = <0x8000>;
62 			d-cache-line-size = <64>;
63 			d-cache-sets = <128>;
64 			next-level-cache = <&L2_0>;
68 			compatible = "arm,cortex-a72";
71 			enable-method = "psci";
72 			i-cache-size = <0xc000>;
73 			i-cache-line-size = <64>;
74 			i-cache-sets = <256>;
75 			d-cache-size = <0x8000>;
76 			d-cache-line-size = <64>;
77 			d-cache-sets = <128>;
78 			next-level-cache = <&L2_0>;
82 	L2_0: l2-cache0 {
83 		compatible = "cache";
84 		cache-level = <2>;
85 		cache-size = <0x100000>;
86 		cache-line-size = <64>;
87 		cache-sets = <2048>;
88 		next-level-cache = <&msmc_l3>;
91 	msmc_l3: l3-cache0 {
92 		compatible = "cache";
93 		cache-level = <3>;
98 			compatible = "linaro,optee-tz";
103 			compatible = "arm,psci-1.0";
108 	a72_timer0: timer-cl0-cpu0 {
109 		compatible = "arm,armv8-timer";
117 		compatible = "arm,armv8-pmuv3";
122 		compatible = "simple-bus";
123 		#address-cells = <2>;
124 		#size-cells = <2>;
150 			compatible = "simple-bus";
151 			#address-cells = <2>;
152 			#size-cells = <2>;
171 #include "k3-j7200-main.dtsi"
172 #include "k3-j7200-mcu-wakeup.dtsi"