Lines Matching +full:cache +full:- +full:sets
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
36 #address-cells = <2>;
37 #size-cells = <0>;
39 cpu-map {
65 idle-states {
66 entry-method = "psci";
68 CPU_SLEEP_0: cpu-sleep-0 {
69 compatible = "arm,idle-state";
70 arm,psci-suspend-param = <0x0010000>;
71 local-timer-stop;
72 entry-latency-us = <300>;
73 exit-latency-us = <1200>;
74 min-residency-us = <2000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
78 compatible = "arm,idle-state";
79 arm,psci-suspend-param = <0x1010000>;
80 local-timer-stop;
81 entry-latency-us = <400>;
82 exit-latency-us = <1200>;
83 min-residency-us = <2500>;
88 compatible = "arm,cortex-a57";
91 enable-method = "psci";
92 i-cache-size = <0xc000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <256>;
95 d-cache-size = <0x8000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <256>;
98 next-level-cache = <&A57_L2>;
100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
101 capacity-dmips-mhz = <1024>;
105 compatible = "arm,cortex-a57";
108 enable-method = "psci";
109 i-cache-size = <0xc000>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <256>;
112 d-cache-size = <0x8000>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <256>;
115 next-level-cache = <&A57_L2>;
117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
118 capacity-dmips-mhz = <1024>;
122 compatible = "arm,cortex-a53";
125 enable-method = "psci";
126 i-cache-size = <0x8000>;
127 i-cache-line-size = <64>;
128 i-cache-sets = <256>;
129 d-cache-size = <0x8000>;
130 d-cache-line-size = <64>;
131 d-cache-sets = <128>;
132 next-level-cache = <&A53_L2>;
134 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
135 capacity-dmips-mhz = <578>;
139 compatible = "arm,cortex-a53";
142 enable-method = "psci";
143 i-cache-size = <0x8000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 d-cache-size = <0x8000>;
147 d-cache-line-size = <64>;
148 d-cache-sets = <128>;
149 next-level-cache = <&A53_L2>;
151 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
152 capacity-dmips-mhz = <578>;
156 compatible = "arm,cortex-a53";
159 enable-method = "psci";
160 i-cache-size = <0x8000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <128>;
166 next-level-cache = <&A53_L2>;
168 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
169 capacity-dmips-mhz = <578>;
173 compatible = "arm,cortex-a53";
176 enable-method = "psci";
177 i-cache-size = <0x8000>;
178 i-cache-line-size = <64>;
179 i-cache-sets = <256>;
180 d-cache-size = <0x8000>;
181 d-cache-line-size = <64>;
182 d-cache-sets = <128>;
183 next-level-cache = <&A53_L2>;
185 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
186 capacity-dmips-mhz = <578>;
189 A57_L2: l2-cache0 {
190 compatible = "cache";
191 cache-size = <0x200000>;
192 cache-line-size = <64>;
193 cache-sets = <2048>;
196 A53_L2: l2-cache1 {
197 compatible = "cache";
198 cache-size = <0x100000>;
199 cache-line-size = <64>;
200 cache-sets = <1024>;
204 pmu-a57 {
205 compatible = "arm,cortex-a57-pmu";
208 interrupt-affinity = <&A57_0>,
212 pmu-a53 {
213 compatible = "arm,cortex-a53-pmu";
218 interrupt-affinity = <&A53_0>,
274 remote-endpoint = <&csys2_funnel_in_port0>;
278 remote-endpoint = <&csys2_funnel_out_port>;
282 remote-endpoint = <&stm_out_port>;
286 remote-endpoint = <&csys1_funnel_in_port0>;