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/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
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/Linux-v5.10/drivers/ata/
Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
25 * struct ftide010 - state container for the Faraday FTIDE010
49 /* Gemini-specific properties */
103 * mdma_50_active_time: array of 4 elements for Td timing for multi
104 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
106 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107 * mdma_66_active_time: array of 4 elements for Td timing for multi
108 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
110 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
114 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
[all …]
Dpata_sch.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sch.c - Intel SCH PATA controllers
10 * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
32 MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
80 MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
86 * sch_set_piomode - Initialize host controller PATA PIO timings
98 unsigned int pio = adev->pio_mode - XFER_PIO_0; in sch_set_piomode()
99 struct pci_dev *dev = to_pci_dev(ap->host->dev); in sch_set_piomode()
100 unsigned int port = adev->devno ? D1TIM : D0TIM; in sch_set_piomode()
109 if (adev->class == ATA_DEV_ATA) in sch_set_piomode()
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/Linux-v5.10/Documentation/i2c/
Dslave-testunit-backend.rst1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
23 After that, you will have a write-only device listening. Reads will just return
24 an 8-bit version number of the testunit. When writing, the device consists of 4
25 8-bit registers and all must be written to start a testcase, i.e. you must
28 0x00 CMD - which test to trigger
29 0x01 DATAL - configuration byte 1 for the test
30 0x02 DATAH - configuration byte 2 for the test
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/Linux-v5.10/sound/soc/sh/rcar/
Dssi.c1 // SPDX-License-Identifier: GPL-2.0
3 // Renesas R-Car SSIU/SSI support
36 #define DWL_MASK (7 << 19) /* Data Word Length mask */
37 #define DWL_8 (0 << 19) /* Data Word Length */
38 #define DWL_16 (1 << 19) /* Data Word Length */
39 #define DWL_18 (2 << 19) /* Data Word Length */
40 #define DWL_20 (3 << 19) /* Data Word Length */
41 #define DWL_22 (4 << 19) /* Data Word Length */
42 #define DWL_24 (5 << 19) /* Data Word Length */
43 #define DWL_32 (6 << 19) /* Data Word Length */
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/Linux-v5.10/fs/ntfs/
Dmst.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * mst.c - NTFS multi sector transfer protection handling code. Part of the
4 * Linux-NTFS project.
6 * Copyright (c) 2001-2004 Anton Altaparmakov
12 * post_read_mst_fixup - deprotect multi sector transfer protected data
16 * Perform the necessary post read multi sector transfer fixup and detect the
17 * presence of incomplete multi sector transfers. - In that case, overwrite the
21 * Return 0 on success and -EINVAL on error ("BAAD" magic will be present).
34 usa_ofs = le16_to_cpu(b->usa_ofs); in post_read_mst_fixup()
36 usa_count = le16_to_cpu(b->usa_count) - 1; in post_read_mst_fixup()
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Dlogfile.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * logfile.c - NTFS kernel journal handling. Part of the Linux-NTFS project.
5 * Copyright (c) 2002-2007 Anton Altaparmakov
27 * ntfs_check_restart_page_header - check the page header for consistency
50 logfile_system_page_size = le32_to_cpu(rp->system_page_size); in ntfs_check_restart_page_header()
51 logfile_log_page_size = le32_to_cpu(rp->log_page_size); in ntfs_check_restart_page_header()
55 (logfile_system_page_size - 1) || in ntfs_check_restart_page_header()
57 ntfs_error(vi->i_sb, "$LogFile uses unsupported page size."); in ntfs_check_restart_page_header()
65 ntfs_error(vi->i_sb, "Found restart area in incorrect " in ntfs_check_restart_page_header()
70 if (sle16_to_cpu(rp->major_ver) != 1 || in ntfs_check_restart_page_header()
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/Linux-v5.10/arch/arm/common/
Dmcpm_head.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
8 * Refer to Documentation/arm/cluster-pm-race-avoidance.rst
126 @ Wait for any previously-pending cluster teardown operations to abort
166 @ In the contended case, non-first men wait here for cluster setup
176 @ If a platform-specific CPU setup hook is needed, it is
203 3: .word mcpm_entry_early_pokes - .
204 .word mcpm_entry_vectors - 3b
205 .word mcpm_power_up_setup_phys - 3b
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/Linux-v5.10/sound/pci/ice1712/
Denvy24ht.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
49 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
60 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
65 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
103 #define VT1724_REG_GPIO_DATA 0x14 /* word */
104 #define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */
106 bit3 - during reset used for Eeprom power-on strapping
114 * Professional multi-track direct control registers
117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
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Dice1712.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/ak4xxx-adda.h>
27 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
31 #define ICE1712_SERR_ASSERT_DS_DMA 0x40 /* disabled SERR# assertion for the DS DMA Ch-C irq ot…
40 #define ICE1712_IRQ_PROPCM 0x10 /* professional multi-track */
41 #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
47 #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
48 #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
61 #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
71 #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
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/Linux-v5.10/Documentation/devicetree/bindings/ata/
Dfaraday,ftide010.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
29 - const: cortina,gemini-pata
30 - const: faraday,ftide010
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/Linux-v5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-inzi.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-INZI:
9 Infrared 10-bit linked with Depth 16-bit images
15 Proprietary multi-planar format used by Intel SR300 Depth cameras, comprise of
16 Infrared image followed by Depth data. The pixel definition is 32-bpp,
22 The first plane - Infrared data - is stored according to
23 :ref:`V4L2_PIX_FMT_Y10 <V4L2-PIX-FMT-Y10>` greyscale format.
24 Each pixel is 16-bit cell, with actual data stored in the 10 LSBs
29 The second plane provides 16-bit per-pixel Depth data arranged in
30 :ref:`V4L2-PIX-FMT-Z16 <V4L2-PIX-FMT-Z16>` format.
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/Linux-v5.10/arch/mips/include/asm/
Dmipsmtregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
202 " .word 0x41610001 # dvpe $1 \n" in dvpe()
220 " .word 0x41600021 # evpe \n" in __raw_evpe()
244 " .word 0x41610BC1 # dmt $1 \n" in dmt()
261 " .word 0x41600be1 # emt \n" in __raw_emt()
266 /* enable multi-threaded execution if previous suggested it should be.
295 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
312 " .word 0x41000820 | (" #rt " << 16) \n" \
339 " .word 0x41810020 | (" #rd " << 11) \n" \
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/Linux-v5.10/Documentation/hwmon/
Dpmbus-core.rst9 power-management protocol with a fully defined command language that facilitates
11 protocol is implemented over the industry-standard SMBus serial interface and
12 enables programming, control, and real-time monitoring of compliant power
18 promoted by the PMBus Implementers Forum (PMBus-IF), comprising 30+ adopters
22 commands, and manufacturers can add as many non-standard commands as they like.
23 Also, different PMBUs devices act differently if non-supported commands are
43 PMBus device capabilities auto-detection
46 For generic PMBus devices, code in pmbus.c attempts to auto-detect all supported
47 PMBus commands. Auto-detection is somewhat limited, since there are simply too
50 pages (see the PMBus specification for details on multi-page PMBus devices).
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/Linux-v5.10/drivers/staging/media/sunxi/cedrus/
Dcedrus_h265.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/videobuf2-dma-contig.h>
22 * implementations, that were initially exposed in libvdpau-sunxi.
46 struct cedrus_dev *dev = ctx->dev; in cedrus_h265_irq_status()
61 struct cedrus_dev *dev = ctx->dev; in cedrus_h265_irq_clear()
68 struct cedrus_dev *dev = ctx->dev; in cedrus_h265_irq_disable()
84 u32 *word = data; in cedrus_h265_sram_write_data() local
87 cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++); in cedrus_h265_sram_write_data()
88 size -= sizeof(u32); in cedrus_h265_sram_write_data()
96 return ctx->codec.h265.mv_col_buf_addr + index * in cedrus_h265_frame_info_mv_col_buf_addr()
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/Linux-v5.10/drivers/net/fddi/skfp/h/
Dfplustm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 __le32 txd_txdscr ; /* transmit frame status word */
59 struct s_txd_os txd_os ; /* OS - specific struct */
67 __le32 rxd_rfsw ; /* receive frame status word */
76 struct s_rxd_os rxd_os ; /* OS - specific struct */
125 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
130 #define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
133 #define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
155 u_short rx_mode ; /* address mode broad/multi/promisc */
228 /* used by the os-specific module */
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/Linux-v5.10/drivers/scsi/csiostor/
Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in csio_t5_pcie_intr_handler()
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/Linux-v5.10/include/linux/spi/
Dspi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
25 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
31 * struct spi_statistics - statistics for spi transfers
34 * @messages: number of spi-messages handled
85 spin_lock_irqsave(&(stats)->lock, flags); \
86 (stats)->field += count; \
87 spin_unlock_irqrestore(&(stats)->lock, flags); \
94 * struct spi_delay - SPI delay information
110 * struct spi_device - Controller side proxy for an SPI slave device
122 * each word in a transfer (by specifying SPI_LSB_FIRST).
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/Linux-v5.10/drivers/crypto/allwinner/sun8i-ce/
Dsun8i-ce-prng.c1 // SPDX-License-Identifier: GPL-2.0
3 * sun8i-ce-prng.c - hardware cryptographic offloader for
6 * Copyright (C) 2015-2020 Corentin Labbe <clabbe@baylibre.com>
12 #include "sun8i-ce.h"
13 #include <linux/dma-mapping.h>
29 memzero_explicit(ctx->seed, ctx->slen); in sun8i_ce_prng_exit()
30 kfree(ctx->seed); in sun8i_ce_prng_exit()
31 ctx->seed = NULL; in sun8i_ce_prng_exit()
32 ctx->slen = 0; in sun8i_ce_prng_exit()
40 if (ctx->seed && ctx->slen != slen) { in sun8i_ce_prng_seed()
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/Linux-v5.10/arch/sh/mm/
Dalignment.c2 * Alignment access counters and corresponding user-space interfaces.
5 * Copyright (C) 2009 - 2010 Paul Mundt
26 /* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
72 if (current->thread.flags & SH_THREAD_UAC_SIGBUS) { in unaligned_user_action()
77 if (current->thread.flags & SH_THREAD_UAC_NOPRINT) in unaligned_user_action()
85 return put_user(tsk->thread.flags & SH_THREAD_UAC_MASK, in get_unalign_ctl()
91 tsk->thread.flags = (tsk->thread.flags & ~SH_THREAD_UAC_MASK) | in set_unalign_ctl()
102 tsk->comm, task_pid_nr(tsk), in unaligned_fixups_notify()
107 tsk->comm, task_pid_nr(tsk), in unaligned_fixups_notify()
125 seq_printf(m, "Word:\t\t%lu\n", se_word); in alignment_proc_show()
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/Linux-v5.10/arch/mips/include/asm/octeon/
Dcvmx-wqe.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
43 #include <asm/octeon/cvmx-packet.h>
102 * - 1 = Malformed L4
103 * - 2 = L4 Checksum Error: the L4 checksum value is
104 * - 3 = UDP Length Error: The UDP length field would
108 * - 4 = Bad L4 Port: either the source or destination
110 * - 8 = TCP FIN Only: the packet is TCP and only the
112 * - 9 = TCP No Flags: the packet is TCP and no flags
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/Linux-v5.10/Documentation/driver-api/i3c/
Dprotocol.rst1 .. SPDX-License-Identifier: GPL-2.0
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
25 while remaining power-efficient.
42 I3C is a multi-master protocol, so there might be several masters on a bus,
51 In addition to these per-device addresses, the protocol defines a broadcast
70 * BCR: Bus Characteristic Register. This 8-bit register describes the device bus
72 * DCR: Device Characteristic Register. This 8-bit register describes the
74 * Provisional ID: A 48-bit unique identifier. On a given bus there should be no
95 I3C Hot-Join
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/Linux-v5.10/drivers/net/ethernet/qualcomm/emac/
Demac-mac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
18 #include "emac-sgmii.h"
210 #define EMAC_SKB_CB(skb) ((struct emac_skb_cb *)(skb)->cb)
217 /* EMAC Errors in emac_rrd.word[3] */
234 #define EMAC_RRD(RXQ, SIZE, IDX) ((RXQ)->rrd.v_addr + (SIZE * (IDX)))
235 #define EMAC_RFD(RXQ, SIZE, IDX) ((RXQ)->rfd.v_addr + (SIZE * (IDX)))
236 #define EMAC_TPD(TXQ, SIZE, IDX) ((TXQ)->tpd.v_addr + (SIZE * (IDX)))
238 #define GET_RFD_BUFFER(RXQ, IDX) (&((RXQ)->rfd.rfbuff[(IDX)]))
239 #define GET_TPD_BUFFER(RTQ, IDX) (&((RTQ)->tpd.tpbuff[(IDX)]))
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/Linux-v5.10/arch/x86/include/asm/
Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 19 /* N 32-bit words worth of info */
17 #define NBUGINTS 1 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
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/Linux-v5.10/tools/arch/x86/include/asm/
Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 19 /* N 32-bit words worth of info */
17 #define NBUGINTS 1 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
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