Lines Matching +full:multi +full:- +full:word
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 19 /* N 32-bit words worth of info */
17 #define NBUGINTS 1 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
78 /* Other features, Linux-defined mapping, word 3 */
94 #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
99 #define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */
103 #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
109 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */
110 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (AP…
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
118 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
120 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
125 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
128 #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
134 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
135 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
144 #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
151 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
152 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
160 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
165 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
167 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
184 #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */
189 * Auxiliary flags: Linux defined - For features scattered in various
190 * CPUID levels like 0x6, 0xA etc, word 7.
202 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
227 /* Virtualization flags: Linux defined, word 8 */
236 #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
239 #define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
241 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
257 #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
258 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
262 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
266 #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
267 #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
268 #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
270 #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
271 #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
273 /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
280 * Extended auxiliary flags: Linux defined - for features scattered in various
292 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
294 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
297 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
306 …MD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
312 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
318 #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
324 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
331 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
339 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
348 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */
350 #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instruct…
353 #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
360 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
365 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
366 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
367 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
369 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
385 * BUG word(s)
400 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
403 #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */