4  * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15  *      - Redistributions of source code must retain the above
19  *      - Redistributions in binary form must reproduce the above
42 	 * Truncation intentional: we only read the bottom 32-bits of the  in csio_t5_set_mem_win()
43 	 * 64-bit BAR0/BAR1 ...  We use the hardware backdoor mechanism to  in csio_t5_set_mem_win()
46 	 * accesses to our Configuration Space and we need to set up the PCI-E  in csio_t5_set_mem_win()
48 	 * coming across the PCI-E link.  in csio_t5_set_mem_win()
60 			  WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),  in csio_t5_set_mem_win()
76 		-1, 1 },  in csio_t5_pcie_intr_handler()
77 		{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
78 		{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
79 		{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
80 		{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
81 		{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
82 		{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
84 		-1, 1 },  in csio_t5_pcie_intr_handler()
86 		-1, 1 },  in csio_t5_pcie_intr_handler()
87 		{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
88 		{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
89 		{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
90 		{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
92 		-1, 1 },  in csio_t5_pcie_intr_handler()
93 		{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
94 		{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
95 		{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
96 		{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
97 		{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
98 		{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
99 		{ FIDPERR_F, "PCI FID parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
100 		{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
101 		{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
102 		{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
104 		-1, 1 },  in csio_t5_pcie_intr_handler()
106 		-1, 1 },  in csio_t5_pcie_intr_handler()
107 		{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
108 		{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
109 		{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },  in csio_t5_pcie_intr_handler()
110 		{ READRSPERR_F, "Outbound read error", -1, 0 },  in csio_t5_pcie_intr_handler()
121  * csio_t5_flash_cfg_addr - return the address of the flash configuration file
134  *      csio_t5_mc_read - read from MC through backdoor accesses
139  *      @ecc: where to store the corresponding 64-bit ECC word
141  *      Read 64 bytes of data from MC starting at a 64-byte-aligned address
143  *      is assigned the 64-bit ECC word for the read data.
159 		return -EBUSY;  in csio_t5_mc_read()
172 	for (i = 15; i >= 0; i--)  in csio_t5_mc_read()
181  *      csio_t5_edc_read - read from EDC through backdoor accesses
186  *      @ecc: where to store the corresponding 64-bit ECC word
188  *      Read 64 bytes of data from EDC starting at a 64-byte-aligned address
190  *      is assigned the 64-bit ECC word for the read data.
203 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)  in csio_t5_edc_read()
214 		return -EBUSY;  in csio_t5_edc_read()
227 	for (i = 15; i >= 0; i--)  in csio_t5_edc_read()
236  * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
238  * @win: PCI-E memory Window to use
247  * 32-bit boudaries.  The memory is transferred as a raw byte sequence
249  * structures which contain multi-byte integers, it's the callers
263 		return -EINVAL;  in csio_t5_memory_rw()
268 	 * MEM_MC   = 2 -- T4  in csio_t5_memory_rw()
269 	 * MEM_MC0  = 2 -- For T5  in csio_t5_memory_rw()
270 	 * MEM_MC1  = 3 -- For T5  in csio_t5_memory_rw()
285 	 * Each PCI-E Memory Window is programmed with a window size -- or  in csio_t5_memory_rw()
286 	 * "aperture" -- which controls the granularity of its mapping onto  in csio_t5_memory_rw()
290 	 * space.  For T4 this is an absolute PCI-E Bus Address.  For T5  in csio_t5_memory_rw()
298 	start = addr & ~(mem_aperture-1);  in csio_t5_memory_rw()
299 	offset = addr - start;  in csio_t5_memory_rw()
300 	win_pf = PFNUM_V(hw->pfn);  in csio_t5_memory_rw()
313 		 * Move PCI-E Memory Window to our current transfer  in csio_t5_memory_rw()
329 			len -= sizeof(__be32);  in csio_t5_memory_rw()
336  * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values