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/Linux-v5.10/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
/Linux-v5.10/Documentation/scsi/
Daic7xxx.rst26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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/Linux-v5.10/drivers/phy/intel/
Dphy-intel-keembay-emmc.c59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
98 if (mhz < 50 || mhz > 200) in keembay_emmc_phy_power()
99 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
124 0, 50); in keembay_emmc_phy_power()
[all …]
/Linux-v5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt15 1 -> 50 us
21 7 -> 50 ms
29 6 -> 50 ms
35 1 -> 50 mA (typical 80 mA max)
53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
79 /* 3.25 MHz ADC clock speed */
100 * 50 mA typical 80 mA max touchscreen drivers
/Linux-v5.10/arch/arm/mach-omap2/
Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
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/Linux-v5.10/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/Linux-v5.10/drivers/ata/
Dpata_ftide010.c80 /* 0 = 50 MHz, 1 = 66 MHz */
95 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
96 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
104 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
106 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
108 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
110 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
112 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
114 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
116 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
[all …]
/Linux-v5.10/drivers/video/fbdev/
Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
72 /* 1024x768, 60 Hz, Non-Interlaced (65.00 MHz dotclock) */
[all …]
/Linux-v5.10/arch/arm/mach-pxa/
Dsleep.S61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
66 @ with core operating above 91 MHz
67 @ (see Errata 50, ...processor does not exit from sleep...)
103 @ about suspending with PXBus operating above 133MHz
123 orrne r7, r7, #1 @@ 99.53MHz
150 @ need 6 13-MHz cycles before changing PWRMODE
151 @ just set frequency to 91-MHz... 6*91/13 = 42
/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dintel_llc.c63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()
69 /* Convert GT frequency to 50 HZ units */ in get_ia_constants()
89 * ring_freq = 2 * GT. ring_freq is in 100MHz units in calc_ia_freq()
94 /* max(2 * GT, DDR). NB: GT is 50MHz units */ in calc_ia_freq()
109 * For GPU frequencies less than 750MHz, in calc_ia_freq()
/Linux-v5.10/drivers/cpufreq/
Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
309 * (200/4=50)->(667/4=166)Mhz in s5pv210_target()
322 * 3. DMC1 refresh count for 133Mhz if (index == L4) is in s5pv210_target()
324 * code. 0x287@83Mhz in s5pv210_target()
375 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ in s5pv210_target()
393 * 7. Change souce clock from SCLKMPLL(667Mhz) in s5pv210_target()
[all …]
Dpxa2xx-cpufreq.c44 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
64 { 99500, -1, -1}, /* 99, 99, 50, 50 */
76 { 99500, -1, -1}, /* 99, 99, 50, 50 */
77 {199100, -1, -1}, /* 99, 199, 50, 99 */
78 {298500, -1, -1}, /* 99, 287, 50, 99 */
202 pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n", in pxa_set_target()
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmicrel.txt22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
/Linux-v5.10/Documentation/admin-guide/media/
Dvivid.rst335 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
358 visible. For 50 Hz standards the top field is the oldest and the bottom field
363 contain the top field for 50 Hz standards and the bottom field for 60 Hz
378 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
379 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
380 will be in color for the +/- 0.25 MHz around it, and in grayscale for
381 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
382 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
386 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
387 a valid channel frequency. When the frequency is within +/- 0.25 MHz of the
[all …]
/Linux-v5.10/drivers/media/pci/mantis/
Dmantis_vp3030.c31 .name = "ENV57H12D5 (ET-50DT)",
33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
/Linux-v5.10/arch/arc/kernel/
Ddevtree.c28 arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */ in arc_set_early_base_baud()
31 arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x & HSDK) */ in arc_set_early_base_baud()
33 arc_base_baud = 50000000; /* Fixed default 50MHz */ in arc_set_early_base_baud()
/Linux-v5.10/drivers/media/tuners/
Dtea5767.c78 /* Japan freq (76-108 MHz. If disabled, 87.5-108 MHz */
81 /* Unselected means 32.768 KHz freq as reference. Otherwise Xtal at 13 MHz */
98 /* By activating, it will use Xtal at 13 MHz as reference for divider */
101 /* By activating, deemphasis=50, or else, deemphasis of 50us */
196 tuner_dbg("radio freq = %d.%03d MHz\n", frq/16000,(frq/16)%1000); in set_radio_freq()
242 tuner_dbg("radio HIGH LO inject xtal @ 13 MHz\n"); in set_radio_freq()
247 tuner_dbg("radio LOW LO inject xtal @ 13 MHz\n"); in set_radio_freq()
252 tuner_dbg("radio LOW LO inject xtal @ 32,768 MHz\n"); in set_radio_freq()
259 tuner_dbg("radio HIGH LO inject xtal @ 32,768 MHz\n"); in set_radio_freq()
354 div = (87500 * 4 + 700 + 225 + 25) / 50; /* Set frequency to 87.5 MHz */ in tea5767_standby()
Dit913x.c50 /* 12.000 MHz */ in it913x_init()
57 /* 20.480 MHz */ in it913x_init()
77 #define TIMEOUT 50 in it913x_init()
99 * Chip version BX never sets that flag so we just wait 50ms in that in it913x_init()
101 * order to get 50ms delay, but that causes about 120 extra I2C in it913x_init()
105 #define TIMEOUT 50 in it913x_init()
120 msleep(50); in it913x_init()
369 .frequency_min_hz = 174 * MHz,
370 .frequency_max_hz = 862 * MHz,
/Linux-v5.10/drivers/clk/
Dclk-ast2600.c74 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
107 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
179 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ in ast2600_calc_pll()
198 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ in ast2600_calc_apll()
523 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
537 /* RMII1 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
545 /* RMII2 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
553 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
567 /* RMII3 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
575 /* RMII4 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
[all …]
/Linux-v5.10/drivers/clk/versatile/
Dclk-icst.c107 * 33 or 25 MHz respectively. in vco_get()
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
267 /* Slam to closest 0.25 MHz */ in icst_round_rate()
273 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
274 * select 25 MHz in icst_round_rate()
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
443 * go to 200 MHz (max VDW = 192).
456 /* Minimum 3 MHz, VDW = 4 */
458 /* Maximum 50 MHz, VDW = 192 */
[all …]
/Linux-v5.10/drivers/scsi/
Ddc395x.h31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
381 /* 000 100ns, 10.0 MHz */
382 /* 001 150ns, 6.6 MHz */
383 /* 010 200ns, 5.0 MHz */
384 /* 011 250ns, 4.0 MHz */
385 /* 100 300ns, 3.3 MHz */
386 /* 101 350ns, 2.8 MHz */
387 /* 110 400ns, 2.5 MHz */
388 /* 111 450ns, 2.2 MHz */
393 /* 000 50ns, 20.0 MHz */
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dam5729-beagleboneai.dts424 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
446 * 50 mA typical 80 mA max touchscreen drivers
557 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
558 /* HS: High speed up to 50 MHz (3.3 V signaling). */
559 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
560 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
561 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
562 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
563 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
/Linux-v5.10/drivers/media/pci/cx18/
Dcx18-firmware.c223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]

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