Lines Matching +full:50 +full:mhz
31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
381 /* 000 100ns, 10.0 MHz */
382 /* 001 150ns, 6.6 MHz */
383 /* 010 200ns, 5.0 MHz */
384 /* 011 250ns, 4.0 MHz */
385 /* 100 300ns, 3.3 MHz */
386 /* 101 350ns, 2.8 MHz */
387 /* 110 400ns, 2.5 MHz */
388 /* 111 450ns, 2.2 MHz */
393 /* 000 50ns, 20.0 MHz */
394 /* 001 75ns, 13.3 MHz */
395 /* 010 100ns, 10.0 MHz */
396 /* 011 125ns, 8.0 MHz */
397 /* 100 150ns, 6.6 MHz */
398 /* 101 175ns, 5.7 MHz */
399 /* 110 200ns, 5.0 MHz */
400 /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
405 /* 000 25ns, 40.0 MHz */
406 /* 001 50ns, 20.0 MHz */
407 /* 010 75ns, 13.3 MHz */
408 /* 011 100ns, 10.0 MHz */
409 /* 100 125ns, 8.0 MHz */
410 /* 101 150ns, 6.6 MHz */
411 /* 110 175ns, 5.7 MHz */
412 /* 111 200ns, 5.0 MHz */
471 /* 50 Initiator transfer information out sequence without ATN */
595 #define CON5068 0x10 /* External 50/68 pin connected (low) */
597 #define CON50 0x04 /* Internal 50 pin connected (low!) */