Lines Matching +full:50 +full:mhz
74 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
107 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
179 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ in ast2600_calc_pll()
198 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ in ast2600_calc_apll()
523 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
537 /* RMII1 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
545 /* RMII2 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
553 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
567 /* RMII3 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
575 /* RMII4 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
755 /* USB 2.0 port1 phy 40MHz clock */ in aspeed_g6_cc()