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/Linux-v5.10/drivers/clk/sunxi-ng/
Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
36 BIT(31), /* gate */
37 BIT(28), /* lock */
45 * With sigma-delta modulation for fractional-N on the audio PLL,
[all …]
Dccu-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
37 .enable = BIT(31),
38 .lock = BIT(28),
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
51 .enable = BIT(31),
52 .lock = BIT(28),
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
66 .enable = BIT(31),
[all …]
Dccu-sun8i-r40.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
36 .hw.init = CLK_HW_INIT("pll-cpu",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
[all …]
Dccu-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a100.h"
26 #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
27 #define SUN50I_A100_PLL_OUTPUT_ENABLE BIT(27)
28 #define SUN50I_A100_PLL_LOCK BIT(28)
29 #define SUN50I_A100_PLL_LOCK_ENABLE BIT(29)
30 #define SUN50I_A100_PLL_ENABLE BIT(31)
51 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
67 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
[all …]
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
51 .lock = BIT(1),
[all …]
Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
23 #include "ccu-sun8i-a23-a33.h"
26 .enable = BIT(31),
27 .lock = BIT(28),
36 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 pll_audio_sdm_table, BIT(24),
66 0x284, BIT(31),
[all …]
Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
49 * With sigma-delta modulation for fractional-N on the audio PLL,
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 pll_audio_sdm_table, BIT(24),
68 0x284, BIT(31),
[all …]
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
29 .enable = BIT(31),
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
63 .enable = BIT(31),
67 0x00c, BIT(31)),
71 .hw.init = CLK_HW_INIT("pll-audio-base",
80 .enable = BIT(31),
[all …]
/Linux-v5.10/drivers/staging/sm750fb/
Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
32 #define DE_DESTINATION_WRAP BIT(31)
43 #define DE_CONTROL_STATUS BIT(31)
44 #define DE_CONTROL_PATTERN BIT(30)
45 #define DE_CONTROL_UPDATE_DESTINATION_X BIT(29)
46 #define DE_CONTROL_QUICK_START BIT(28)
47 #define DE_CONTROL_DIRECTION BIT(27)
48 #define DE_CONTROL_MAJOR BIT(26)
49 #define DE_CONTROL_STEP_X BIT(25)
[all …]
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/Linux-v5.10/arch/alpha/lib/
Ddivide.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
22 * $24 and $25, and return the result in $27. Register $28 may
27 * This is a rather simple bit-at-a-time algorithm: it's very good
28 * at dividing random 64-bit numbers, but the more usual case where
37 * $0 - current bit
[all …]
Dev6-divide.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-divide.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
22 * $24 and $25, and return the result in $27. Register $28 may
27 * This is a rather simple bit-at-a-time algorithm: it's very good
[all …]
/Linux-v5.10/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
[all …]
/Linux-v5.10/drivers/gpu/drm/vc4/
Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 ((2 << 24) | \
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
53 # define V3D_SLCACTL_T1CC_SHIFT 24
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/Linux-v5.10/drivers/gpu/drm/tve200/
Dtve200_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
[all …]
/Linux-v5.10/drivers/net/ethernet/amazon/ena/
Dena_eth_io_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
24 /* 15:0 : length - Buffer length in bytes, must
26 * to update like End-to-End CRC, Authentication GMAC
29 * the 4-byte added in the end for 802.3 Ethernet FCS
30 * 21:16 : req_id_hi - Request ID[15:10]
31 * 22 : reserved22 - MBZ
32 * 23 : meta_desc - MBZ
33 * 24 : phase
34 * 25 : reserved1 - MBZ
[all …]
/Linux-v5.10/drivers/net/phy/mscc/
Dmscc_macsec.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define CONTROL_IV0 BIT(5)
18 #define CONTROL_IV1 BIT(6)
19 #define CONTROL_IV2 BIT(7)
20 #define CONTROL_UPDATE_SEQ BIT(13)
21 #define CONTROL_IV_IN_SEQ BIT(14)
22 #define CONTROL_ENCRYPT_AUTH BIT(15)
23 #define CONTROL_KEY_IN_CTX BIT(16)
33 #define CONTROL_SEQ_MASK BIT(30)
34 #define CONTROL_CONTEXT_ID BIT(31)
[all …]
/Linux-v5.10/sound/soc/fsl/
Dfsl_sai.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
44 #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
71 #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
88 #define FSL_SAI_CSR_TERE BIT(31)
89 #define FSL_SAI_CSR_SE BIT(30)
90 #define FSL_SAI_CSR_FR BIT(25)
91 #define FSL_SAI_CSR_SR BIT(24)
96 #define FSL_SAI_CSR_WSF BIT(20)
97 #define FSL_SAI_CSR_SEF BIT(19)
[all …]
/Linux-v5.10/drivers/media/platform/vsp1/
Dvsp1_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/Linux-v5.10/drivers/staging/media/hantro/
Dhantro_g1_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24)
17 #define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18)
18 #define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
19 #define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16)
20 #define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15)
21 #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
22 #define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13)
23 #define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12)
24 #define G1_REG_INTERRUPT_DEC_IRQ BIT(8)
[all …]
/Linux-v5.10/drivers/media/platform/exynos4-is/
Dfimc-lite-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include "fimc-lite.h"
24 #define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24)
25 #define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24)
26 #define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24)
27 #define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24)
28 #define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24)
30 #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
31 #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24)
32 #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21)
[all …]
/Linux-v5.10/drivers/media/cec/platform/tegra/
Dtegra_cec.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
[all …]
/Linux-v5.10/sound/soc/hisilicon/
Dhi6210-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
20 #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT 24
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
[all …]

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