Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
77 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
81 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
83 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
84 #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
86 #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
87 #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
89 #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
90 #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
92 #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
95 #define IMX6Q_GPR1_PCIE_SW_RST BIT(29)
96 #define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
97 #define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
98 #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
99 #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
100 #define IMX6Q_GPR1_DPI_OFF BIT(24)
101 #define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
103 #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
104 #define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
106 #define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
107 #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
109 #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
110 #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
112 #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
113 #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
114 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
116 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
117 #define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
118 #define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
119 #define IMX6Q_GPR1_PCIE_INT BIT(14)
120 #define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
122 #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
123 #define IMX6Q_GPR1_GINT BIT(12)
128 #define IMX6Q_GPR1_ACT_CS3 BIT(9)
130 #define IMX6Q_GPR1_ACT_CS2 BIT(6)
132 #define IMX6Q_GPR1_ACT_CS1 BIT(3)
134 #define IMX6Q_GPR1_ACT_CS0 BIT(0)
150 #define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
152 #define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
153 #define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
155 #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
156 #define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
158 #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
159 #define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
161 #define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
162 #define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
164 #define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
165 #define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
167 #define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
168 #define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
170 #define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
171 #define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
185 #define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
186 #define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
187 #define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
188 #define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
191 #define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
192 #define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
193 #define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
194 #define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
195 #define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
196 #define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
197 #define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
221 #define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
222 #define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
223 #define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
224 #define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
225 #define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
226 #define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
227 #define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
228 #define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
229 #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
230 #define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
231 #define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
232 #define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
235 #define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
236 #define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
237 #define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
238 #define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
239 #define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
240 #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
242 #define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
243 #define IMX6Q_GPR5_SATA_SW_PD BIT(10)
244 #define IMX6Q_GPR5_SATA_SW_RST BIT(11)
252 #define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24)
261 #define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24)
270 #define IMX6Q_GPR9_TZASC2_BYP BIT(1)
271 #define IMX6Q_GPR9_TZASC1_BYP BIT(0)
273 #define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
274 #define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
275 #define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
277 #define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
280 #define IMX6Q_GPR10_DBG_EN BIT(13)
281 #define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
282 #define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
284 #define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
286 #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
298 #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
299 #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
300 #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
301 #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
303 #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
306 #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
307 #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
308 #define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
309 #define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
310 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
311 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
312 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
313 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
314 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
315 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
316 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
317 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
318 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
331 #define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
333 #define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
334 #define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
392 #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
393 #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
414 #define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24)
415 #define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24)
434 #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19)
448 #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30)
449 #define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)